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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5378 low-power single-chann el decimation filter features z single-channel digital decimation filter ? multiple on-chip fir and iir coefficient sets ? programmable coefficients for custom filters ? synchronous operation z integrated pll for clock generation ? 1.024 mhz, 2.048 mhz, or 4.096 mhz input ? standard clock or manchester input z selectable output word rate ? 4000, 2000, 1000, 500, 333, 250 sps ? 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 sps z digital gain and offset corrections z test dac bit-st ream generator ? sine wave or impulse output mode z time break controller , general-purpose i/o z microcontroller or e eprom configuration z small-footprint, 28-pin ssop package z low power consumption ? 16 mw at 500 sps owr z flexible power supplies ? i/o interface and pll: 3.3 v or 5.0 v ? digital logic core: 2.5 v, 3.3 v or 5.0 v description the cs5378 is a multi-function digital filter utilizing a low- power signal processing architecture to achieve efficient filtering for a delta-sigma-type modulator. by combining the cs5378 with a cs3301/02 differential amplifier, a cs5371 modulator, and a cs4373 test dac, a synchro- nous high-resolution measurement system can be designed quickly and easily. digital filter coefficients for the cs5378 fir and iir filters are included on-chip for a simple setup, or they can be programmed for custom applications. selectable digital filter decimation ratios produce output word rates from 4000 sps to 1 sps, resulting in measurement band- widths ranging from 1600 hz down to 400 mhz when using the on-chip coefficient sets. the cs5378 includes integrated peripherals to simplify system design: a low-jitter pll for standard clock or manchester inputs, offset and gain corrections, a test dac bit stream generator, a time break controller, and eight general-purpose i/o pins. ordering in formation see page 86 . i serial interface decimation and filtering engine modulator data interface test bit stream controller reset, synchronization tbsdata time break controller gpio general purpose i/o sck mosi vddpad vddpll vddcore sync msync timeb gpio5:pll1 gpio4:pll0 gpio3 gpio2 gpio1 gndpad gndcore gndpll mdata mflag gpio0 gpio6:pll2 gpio7:boot drdy miso ss:eecs reset clk mclk pll, clock generation oct ?05 ds639f1
cs5378 ds639f1 2 table of contents 1. general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. digital filter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2. integrated peripheral features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3. system level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4. configuration interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2. characteristics and specific ations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 specified operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. system design with cs5378 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2. reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3. pll and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.4. synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.5. system configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.6. digital filter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.7. data collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.8. integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4. power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2. bypass capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3. power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5. reset control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.2. reset self-tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.3. boot configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6. pll and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.2. pll mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.3. synchronous clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.4. master clock jitter and skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7. synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7.2. msync generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7.3. digital filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7.4. modulator synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 7.5. test bit stream synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 8. configuration by eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8.2. eeprom hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8.3. eeprom organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8.4. eeprom configuration commands . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8.5. example eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 9. configuration by microcontr oller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
cs5378 ds639f1 3 9.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9.2. microcontroller hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9.3. microcontroller serial trans actions . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9.4. microcontroller configuration commands . . . . . . . . . . . . . . . . . . . . . . .33 9.5. example microcontroller configuration . . . . . . . . . . . . . . . . . . . . . . . . .35 10. modulator interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 10.2. modulator clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 10.3. modulator synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 10.4. modulator data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 10.5. modulator flag input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 11. digital filter initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.1. filter coefficient selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 11.2. filter configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 12. sinc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1. sinc1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 12.2. sinc2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 12.3. sinc3 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 12.4. sinc filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 13. fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.1. fir1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 13.2. fir2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 13.3. on-chip fir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 13.4. programmable fir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 13.5. fir filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 14. iir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.1. iir architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14.2. iir1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14.3. iir2 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14.4. iir3 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 14.5. on-chip iir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 14.6. programmable iir coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 14.7. iir filter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 15. gain and offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.1. gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.2. offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 15.3. offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 16. serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.2. serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 16.3. serial data transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 17. test bit stream generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.2. tbs architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.3. tbs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 17.4. tbs data source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 17.5. tbs sine wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 17.6. tbs impulse output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
cs5378 ds639f1 4 17.7. tbs loopback testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 17.8. tbs synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 18. time break controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 18.1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.2. time break operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 18.3. time break delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 19. general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 19.2. gpio architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 19.3. gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 19.4. gpio input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 19.5. gpio output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 20. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.1. spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 20.2. digital filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 21. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 22. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 23. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24. environmental, manufac turing, & handling informat ion . . . . . . . . . . 86 25. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 list of figures figure 1. cs5378 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. digital filtering stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. fir and iir coefficient set selection word . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. mosi write timing in spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. miso read timing in spi slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. serial data read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. sync, mclk, msync, mdata interface timing. . . . . . . . . . . . . . . . . . . . . 16 figure 8. tbs output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. single-channel system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. power supply block diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. reset control bl ock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. clock generation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. synchronization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. eeprom configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. eeprom serial read transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. 8 kbyte eeprom memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. serial interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. microcontroller serial tr ansactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. modulator data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. digital filter stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. fir and iir coefficient set selection word . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23. sinc filter blo ck diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24. sinc filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. fir filter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 26. fir filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
cs5378 ds639f1 5 figure 27. fir1 coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 28. fir2 linear phase coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 29. fir2 minimum phase coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 30. iir filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 31. iir filter stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 32. gain and offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 33. serial data interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 34. 32-bit serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 35. sd port transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 36. test bit stream genera tor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 37. time break block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 38. gpio block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 39. spi control register spictrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 40. spi command register spicmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 41. spi data register spidat1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 42. spi data register spidat2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 43. hardware configuratio n register config. . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 44. gpio configuration register gpcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 45. filter configuration re gister filtcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 46. gain correction register gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 47. offset correction register offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 48. time break counter register timebrk . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 49. test bit stream configuration register tbscfg. . . . . . . . . . . . . . . . . . . . . 78 figure 50. test bit stream gain register tbsgain . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 51. user defined system register system1 . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 52. hardware version id register version . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 53. self test result regi ster selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 54. cs5378 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 list of tables table 1. microcontro ller and eeprom configuration commands . . . . . . . . . . . . . . . . . 9 table 2. tbs configurations using on-chip data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. spi and digital filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. pll and boot mode reset configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. pll mode selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. maximum eeprom configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. eeprom boot configuration commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. example eeprom file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. microcontroller boot configuration comman ds . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. example microcontroller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. sinc filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 12. sinc1 and sinc2 filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13. sinc3 filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 14. fir filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15. sinc + fir group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 16. minimum phase group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. iir filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17. iir filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18. tbs configurations using on-chip data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19. tbs impulse characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
cs5378 ds639f1 6 1. general description the cs5378 is a single ch annel digital filter with integrated system periphera ls. figure 1 illustrates a simplified block diagram of the cs5378. 1.1 digital filter features ? single channel decimation filter for cs5371 ? modulator. ? synchronous operation for simultaneous sam- pling in multi-sensor systems. - internal synchronizati on of digital filter phase to an external sync signal. ? output word rates, including low bandwidth rates. - standard output rates: 4000, 2000, 1000, 500, 333, 250 sps. - low bandwidth rates: 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 sps. ? flexible digital filter configuration. (see figure 2) - cascaded sinc, fir, and iir filters with selectable output stage. - linear and minimum phase fir low-pass filter coefficients included. - 3 hz butterworth iir hi gh-pass filter coef- ficients included. - fir and iir coeffici ents programmable to create a custom filter response. ? digital gain correcti on to normalize sensor gain. ? digital offset correction and calibration. - offset correction to remove measurement serial interface decimation and filtering engine modulator data interface test bit stream controller reset, synchronization tbsdata time break controller gpio general purpose i/o sck mosi vddpad vddpll vddcore sync msync timeb gpio5:pll1 gpio4:pll0 gpio3 gpio2 gpio1 gndpad gndcore gndpll mdata mflag gpio0 gpio6:pll2 gpio7:boot drdy miso ss:eecs reset clk mclk pll, clock generation figure 1. cs5378 block diagram
cs5378 ds639f1 7 dc offset. - calibration engine for automatic calcula- tion of offset correction factor. 1.2 integrated peripheral features ? low jitter pll to ge nerate local clocks. - 1.024 mhz, 2.048 mhz, 4.096 mhz stan- dard clock or manchester encoded input. ? synchronous operation for simultaneous sam- pling in multi-sensor systems. - mclk / msync output signals to syn- chronize external components. ? high speed serial data output. - asynchronous operation to 4 mhz for di- rect connection to system telemetry. - internal 8-deep data fifo for flexible out- put timing. - selectable 24-bit data only or 32-bit sta- tus+data output. ? digital test bit stream signal generator suitable for cs4373 ? test dac. - sine wave output mode for testing total har- monic distortion. - impulse output mode for transfer function characterization. ? time break controller to record system timing information. - dedicated tb status bit in the output data stream. - programmable output delay to match sys- tem group delay. ? 8 general purpose i/o (gpio) pins for local hardware control. 1.3 system level features ? flexible configuration options. - configuration 'on-the- fly' via microcontrol- ler or system telemetry. - fixed configuration via stand-alone boot eeprom. ? low power consumption. - 16 mw at 500 sps owr. - 100 w standby mode. ? flexible power supply configurations. - separate digital logi c core, telemetry i/o, figure 2. digita l filtering stages sinc filter 2 - 64000 fir1 4 fir2 2 iir1 iir2 1 st order 2 nd order output to high speed serial interface dc offset corrections output word rate from 4000 sps ~ 1 sps gain & modulator 512 khz input
cs5378 ds639f1 8 and pll power supplies. - telemetry i/o and pll interfaces operate from 3.3 v or 5 v. - digital logic core operates from 2.5 v, 3.3 v or 5 v. ? small 28-pin ssop package. - total footprint 8 mm x 10 mm plus three bypass capacitors. 1.4 configuration interface ? configuration from micr ocontroller or stand- alone boot eeprom. - microcontroller boot permits reconfigura- tion during operation. - eeprom boot sets a fixed operational con- figuration. ? configuration commands written through the serial interface. (see table 1) - standardized microcont roller interface us- ing spi registers. (see table 3) - commands write digital filter registers and fir / iir filter coefficients. - digital filter registers set hardware config- uration options.
cs5378 ds639f1 9 microcontroller boot configuration commands eeprom boot configuration commands [data] indicates data word returned from digital filter. (data) indicates multiple words of this type are to be written. name cmd 24-bit dat1 24-bit dat2 24-bit description nop 000000 - - no operation write df register 000001 reg data write digital filter register read df register 000002 reg [data] - - read digital filter register write fir coefficients 000003 num fir1 (fir coef) num fir2 (fir coef) write custom fir coefficients write iir coefficients 000004 a11 b11 a22 b21 b10 a21 b20 b22 write custom iir coefficients write rom coefficients 000005 coef sel - use on-chip coefficients nop 000006 - - no operation nop 000007 - - no operation filter start 000008 - - start digital filter operation filter stop 000009 - - stop digital filter operation name cmd 8-bit data 24-bit description nop 00 - no operation write df register 01 reg data write digital filter register write fir coefficients 02 num fir1 num fir2 (fir coef) write custom fir coefficients write iir coefficients 03 a11 b10 b11 a21 a22 b20 b21 b22 write custom iir coefficients write rom coefficients 04 coef sel use on-chip coefficients nop 05 - no operation nop 06 - no operation filter start 07 - start digital filter operation table 1. microcontroller and eeprom configuration commands
cs5378 ds639f1 10 bits 23:20 19:16 15:12 11:8 7:4 3:0 selection 0000 0000 iir2 iir1 fir2 fir1 figure 3. fir and iir coef ficient set selection word bits 15:12 iir2 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 11:8 iir1 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 7:4 fir2 coefficients 0000 linear phase 0001 minimum phase bits 3:0 fir1 coefficients 0000 linear phase 0001 minimum phase test bit stream charac teristic equation: (signal freq) * (# tbs data) * (interpolation + 1) = output rate example: (31.25 hz) * (1024) * (0x07 + 1) = 256 khz signal frequency (tbsdata) output rate (tbsclk) output rate selection (rate) interpolation selection (intp) 10.00 hz 256 khz 0x4 0x18 10.00 hz 512 khz 0x5 0x31 25.00 hz 256 khz 0x4 0x09 25.00 hz 512 khz 0x5 0x13 31.25 hz 256 khz 0x4 0x07 31.25 hz 512 khz 0x5 0x0f 50.00 hz 256 khz 0x4 0x04 50.00 hz 512 khz 0x5 0x09 125.00 hz 256 khz 0x4 0x01 125.00 hz 512 khz 0x5 0x03 table 2. tbs configurations using on-chip data
cs5378 ds639f1 11 spi registers digital filter registers name addr. type # bits description spictrl 00 - 02 r/w 8, 8, 8 spi control spicmd 03 - 05 r/w 8, 8, 8 spi command spidat1 06 - 08 r/w 8, 8, 8 spi data 1 spidat2 09 - 0b r/w 8, 8, 8 spi data 2 name addr. type # bits description config 00 r/w 24 hardware configuration reserved 01-0d r/w 24 reserved gpcfg 0e r/w 24 gpio[7:0] direction, pull-up enable, and data reserved 0f-1f r/w 24 reserved filtcfg 20 r/w 24 digital filter configuration gain 21 r/w 24 gain correction reserved 22-24 r/w 24 reserved offset 25 r/w 24 offset correction reserved 26-28 r/w 24 reserved timebrk 29 r/w 24 time break delay tbscfg 2a r/w 24 test bit stream configuration tbsgain 2b r/w 24 test bit stream gain system1 2c r/w 24 user defined system register 1 system2 2d r/w 24 user defined system register 2 version 2e r/w 24 hardware version id selftest 2f r/w 24 self-test result code table 3. spi and di gital filter registers table 4. pll and boot mode reset configurations pll[2:0] mode selection on reset 111 32.768 mhz clock input (pll bypass). 110 1.024 mhz clock input. 101 2.048 mhz clock input. 100 4.096 mhz clock input. 011 32.768 mhz clock input (pll bypass). 010 1.024 mhz manchester input. 001 2.048 mhz manchester input. 000 4.096 mhz manchester input. configuration note: states of the pll[2:0] and boot pins are latched immediately after reset to select modes. these pins have a weak (~100 k ? ) pull-up re- sistor enabled by default. an external 10 k ? pull-down is required to set a low condition. boot mode selection on reset 1 eeprom boot 0 microcontroller boot
cs5378 ds639f1 12 2. characteristics and specifications ? min / max characteristics and specifications ar e guaranteed over the specified operating conditions. ? typical performance charac teristics and specifications are deri ved from measuremen ts taken at nomi- nal supply voltages and t a = 25 c. ? gnd, gnd1, gnd2 = 0 v, all voltages with respect to 0 v. specified operat ing conditions absolute maximum ratings 1. transient currents up to 100 ma will not cause scr latch-up. parameter symbol min nom max unit logic core power supply vddcore 2.375 2.5 5.25 v pll power supply vddpll 3.135 3.3 5.25 v i/o power supply vddpad 3.135 3.3 5.25 v ambient operating temperature industrial (-iq) t a -40 - 85 c parameter symbol min max units dc power supplies logic core pll i/o vddcore vddpll vddpad -0.3 -0.3 -0.3 6.0 6.0 6.0 v v v input current, any pin ex cept supplies (note 1) i in -10ma input current, powe r supplies (note 1) i in -50ma output current (note 1) i out -25ma power dissipation p dn -500mw digital input voltages v ind -0.3 vdd+0.3 v ambient operating temperature (power applied) t a -40 85 c storage temperature range t stg -65 150 c
cs5378 ds639f1 13 thermal characteristics digital characteristics notes: 2. maximum leakage for pins with pull-up resistors (reset , ss:eecs , gpio, mosi, sck) is 250 a. power consumption parameter symbol min typ max unit allowable junction temperature t j --135c junction to ambient thermal impedance (4-layer pcb) ja -50 c / w ambient operating temperature (power applied) t a -40 - +85 c parameter symbol min typ max unit high-level input drive voltage v ih 0.6 * vdd - vdd v low-level input drive voltage v il 0.0 - 0.8 v high-level output drive voltage i out = -40 a v oh vdd - 0.3 - vdd v low-level output drive voltage i out = +40 a v ol 0.0 - 0.3 v rise times, digital inputs t rise --100ns fall times, digital inputs t fall --100ns rise times, digital outputs t rise --100ns fall times, digital outputs t fall --100ns input leakage current (note 2) i in - 1 10a 3-state leakage current i oz -- 10a digital input capacitance c in -9-pf digital output pin capacitance c out -9-pf parameter symbol min typ max unit operational power consumption 1.024 mhz digital filter clock pwr 1 -12-mw 2.048 mhz digital filter clock pwr 2 -14-mw 4.096 mhz digital filter clock pwr 4 -16-mw 8.192 mhz digital filter clock pwr 8 -24-mw standby power consumption 32 khz digital filter clock, filter stopped pwr s - 100 - w 2.6 v 0.7 v t fa llin t risein 4.6 v 0.4 v t riseout t fallout 0.90 * vdd 0.10 * vdd 0.90 * vdd 0.10 * vdd
cs5378 ds639f1 14 switching characteristics serial configuration interface timing (external master) parameter symbol min typ max unit mosi write timing ss:eecs enable to valid latch clock t 1 60 - - ns data set-up time prior to sck rising t 2 60 - - ns data hold time after sck rising t 3 120 - - ns sck high time t 4 120 - - ns sck low time t 5 120 - - ns sck falling prior to ss:eecs disable t 6 60 - - ns miso read timing sck falling to new data bit t 7 --200ns sck high time t 8 120 - - ns sck low time t 9 120 - - ns ss:eecs rising to miso hi-z t 10 --150ns figure 4. mosi write ti ming in spi slave mode ssi mosi sclk msb msb - 1 lsb t 6 t 5 t 4 t 3 t 2 t 1 sck ss:eecs figure 5. miso read ti ming in spi slave mode miso sclk msb msb - 1 lsb t 10 t 9 t 8 t 7 ssi ss:eecs sck
cs5378 ds639f1 15 switching characteristics serial data interface timing parameter symbol min typ max unit drdy falling edge to sck rising t 1 60 - - ns sck falling to new data bit t 2 --120ns sck high time t 3 120 - - ns sck low time t 4 120 - - ns final sck falling to drdy rising t 5 60 - - ns figure 6. serial data read timing miso sck t 3 drdy t 4 t 2 t 1 t 5
cs5378 ds639f1 16 switching characteristics clk, sync, mclk, msync, and mdata notes: 3. pll bypass mode. the pll generates a 32.768 mhz master clock when enabled. 4. sampling synchronization between multiple cs 5378 devices receiving identical sync signals. parameter symbol min typ max unit master clock frequency (note 3) clk 32 32.768 33 mhz master clock duty cycle dty 40 - 60 % master clock rise time t rise - - 20 ns master clock fall time t fall - - 20 ns master clock jitter jtr - - 300 ps synchronization after sync rising (note 4) sync -2 - 2 s msync setup time to mclk rising t mss 20 - - ns mclk rising to valid mdata t mdv - - 75 ns msync falling to mclk rising t msf 20 - - ns msync mclk mdata figure 7. sync, mclk, ms ync, mdata interface timing t msd t msd t msh data1 data2 sync f mclk 2.048 mhz 1.024 mhz t msd = t mclk / 4 t msd = 122 ns t msd = 244 ns t msh = t mclk t msh = 488 ns t msh = 976 ns note: sync input latched on mclk rising edge. msync output triggered by mclk falling edge.
cs5378 ds639f1 17 switching characteristics test bit stream (tbs) 5. tbsdata can be delayed from 0 to 63 full bit periods. the timing diagram shows no tbsdata delay. parameter symbol min typ max unit tbs data output timing tbs data bit rate - 256 - kbps tbs data rising to mclk rising setup time t 1 60 - - ns mclk rising to tbs data falling hold time (note 5) t 2 60 - - ns figure 8. tbs ou tput data timing tbsdata mclk t 2 t 1 note: example timing shown for a 256 khz output rate and no pr ogrammable delays.
cs5378 ds639f1 18 3. system design with cs5378 figure 9 illustrates a simplified block diagram of the cs5378 in a single ch annel measurement sys- tem. a differential sensor is connected through the cs3301/02 differential am plifiers to the cs5371 ? modulator, where analog to digital conversion occurs. the modulator?s 1-bit output connects to the cs5378 mdata input, where the oversam- pled ? data is decimated and filtered to 24-bit out- put samples at a program med output rate. these output samples are buffered into an 8-deep data fifo and then passed to the system telemetry. system self tests are performed by connecting the cs5378 test bit stream (tbs) generator to the cs4373 test dac. analog te sts drive differential signals from the cs4373 test dac into the multi- plexed inputs of the cs33 01/02 amplifiers or di- rectly to the differentia l sensor. digital loopback tests internally connect the tbs digital output di- rectly to the cs5378 modulator input. 3.1 power supplies the system shown in figure 9 typically operates from a 2.5 v or a 5 v analog power supply and a 3.3 v digital power supply. the cs5378 logic core can be powered from 2.5 v to minimize power con- sumption, if required. 3.2 reset control system reset is required only for the cs5378 de- vice, and is a standard active low signal that can be generated by a power suppl y monitor or microcon- troller. other system de vices default to a power- down state when the cs5378 is reset. 3.3 pll and clock generation a pll is included on the cs 5378 to generate an in- ternal 32.768 mhz mast er clock from a 1.024 mhz, 2.048 mhz, or 4.096 mhz standard clock or manchester en coded input. clock inputs for other system devices are driven by clock out- puts from the cs5378. digital filter w/ pll amp geophone or hydrophone sensor m u x controller or configuration eeprom communication interface cs3301 cs3302 cs5378 system telemetry ? modulator cs5371 ? test dac cs4373 figure 9. single-channel system block diagram
cs5378 ds639f1 19 3.4 synchronization digital filter phase and analog sample timing of the ? modulator connected to the cs5378 are syn- chronized by a rising edge on the sync pin. if a synchronization signal is re ceived identically by all cs5378 devices in a meas urement network, syn- chronous sampling across the network is guaran- teed. 3.5 system configuration through the serial configur ation interface, filter coefficients and digital fi lter register settings can either be programmed by a microcontroller or auto- matically loaded from an external eeprom after reset. system configurat ion is only required for the cs5378 device, as other devi ces are configured via the cs5378 general purpose i/o pins. two registers in the dig ital filter, system1 and system2 (0x2c, 0x2d), are provided for user de- fined system informati on. these are general pur- pose registers that will hol d any 24-bit data values written to them. 3.6 digital filter operation after analog to digital conversion occurs in the modulator, the oversampled 1-bit ? data is read into the cs5378 through the mdata pin. the dig- ital filter then processe s data through the enabled filter stages, decimating it to 24-bit words at a pro- grammed output word rate . the final 24-bit sam- ples are concatenated with 8-bit status words and placed into an output fifo. 3.7 data collection data is collected from the cs5378 through the se- rial data interface. when data is available, serial transactions are automatica lly initiated to transfer 24-bit data or 32-bit st atus+data from the output fifo to the system teleme try. the output fifo has eight data locations to permit latency in data collec- tion. 3.8 integrated peripherals test bit stream (tbs) a digital signal generato r built into the cs5378 produces a 1-bit ? sine wave or impulse function. this digital test bit stream is connected to the cs4373 test dac to create high quality analog test signals or internally looped back to the cs5378 mdata input to test the di gital filter and data col- lection circuitry. time break timing information is reco rded during data collec- tion by strobing the timeb pin. a dedicated flag in the sample status bits, tb, is set high to indicate during which measuremen t the timing event oc- curred. general purpose i/o (gpio) eight general purpose pins are available on the cs5378 for system control. each pin can be set as input or output, high or lo w, with an internal pull- up enabled or disabled. the cs3301/02, cs5371 and cs4373 devices in fi gure 9 are configured by simple pin settings controlled through the cs5378 gpio pins.
cs5378 ds639f1 20 4. power supplies the cs5378 has three sets of power supply inputs. one set supplies power to th e i/o pins of the device (vddpad), another supplies power to the logic core (vddcore) and the third supplies power to the pll (vddpll). the i/o pin power supplies determine the maximum input and output voltages when interfacing to peripher als, the logic core pow- er supply largely determ ines the power consump- tion of the cs5378 and the pll power supply powers the internal pll circuitry. 4.1 pin descriptions vddpad, gndpad - pins 9, 10 sets the interface voltage to a microcontroller, sys- tem telemetry, modulator , and test dac. vdd- pad can be driven with voltages from 3.3 v to 5v. vddpll, gndpll - pins 15, 16 sets the operational voltage of the internal cs5378 pll circuitry. can be dr iven with voltages from 3.3 v to 5 v. vddcore, gndcore - pins 21, 22 sets the operational vo ltage of the cs5378 logic core. vddcore can be dr iven with voltages from 2.5 v to 5 v. a 2.5 v suppl y will minimize total power consumption. 4.2 bypass capacitors each power supply pin should be bypassed with parallel 1 f and 0.01 f caps, or by a single 0.1 f cap, placed as close as possible to the cs5378. bypass capacitors should be ceramic (x7r, c0g), tantalum, or other good quality di- electric type. 4.3 power consumption power consumption of the cs5378 depends prima- rily on the power supply voltage of the logic core (vddcore) and the programmed digital filter clock rate. digital filter clock rates are selected based on the required output word rate as explained in ?digital filter in itialization? on page 38. 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 vddpad gndpad gndcore vddcore figure 10. power su pply block diagram gndpll vddpll
cs5378 ds639f1 21 5. reset control the cs5378 reset signal is active low. when re- leased, a series of self-t ests are performed and the device either actively boot s from an external ee- prom or enters an idle state waiting for microcon- troller configuration. 5.1 pin descriptions reset - pin 18 reset input, active low. gpio7:boot - pin 28 boot mode select, latche d immediately following reset. weak (~100 k ? ) internal pull-up defaults high, external 10 k ? pull-down required to set low. 5.2 reset self-tests after reset is released but be fore booting, a se- ries of digital filter self -tests are run. results are combined into the selftest register (0x2f), with 0x0aaaaa indicating all passed. self-tests require 60 ms to complete. 5.3 boot configurations the logic state of the b oot pin after reset deter- mines if the cs5378 activ ely reads configuration information from eeprom or enters an idle state waiting for a microcontrolle r to write configuration commands. eeprom boot when the boot pin is hi gh after reset, the cs5378 actively reads data from an external serial ee- prom and then begins operation in the specified configuration. configur ation commands and data are encoded in the eeprom as specified in the ?configuration by eeprom? section of this data sheet, starting on page 25. microcontroller boot when the boot pin is low after reset, the cs5378 enters an idle state wait ing for a microcontroller to write configuration comma nds and initialize filter operation. configuration commands and data are written as specified in the ?configuration by mi- crocontroller? secti on of this data sheet, starting on page 30. reset self-tests selftest register boot pin eeprom boot controller boot 1 0 figure 11. reset control block diagram boot reset mode 1 eeprom boot 0 microcontroller boot self-test type pass code fail code program rom 0x00000a 0x00000f data rom 0x0000a0 0x0000f0 program ram 0x000a00 0x000f00 data ram 0x00a000 0x00f000 execution unit 0x0a0000 0x0f0000
cs5378 ds639f1 22 6. pll and clock generation the cs5378 requires a 32.768 mhz master clock, which can be supplied direct ly or from an internal phase locked loop. this master clock is used to generate an internal digita l filter clock and an exter- nal modulator clock. the internal pll will lo ck to standard clock or manchester encoded input signals. the input type and input frequency are se lected by the reset state of the pll mode select pins. 6.1 pin descriptions clk - pin 17 clock or pll input, standard clock or manchester. gpio[4:6]:pll[0:2] - pins 5, 6, 7 pll mode select, latched immediately after reset. weak (~100 k ? ) internal pull-ups default high, ex- ternal 10 k ? pull-downs required to set low. 6.2 pll mode select the cs5378 pll operational mode and frequency are selected imme diately after reset based on the state of the pll[0:2] pins. on the rising edge of the reset signal, the digital high or low state of the pll[0:2] pins is latched and used to program the clock input type and frequency. a weak internal pull-up resistor (~100 k ? ) will hold the pll mode select pins high by default. to force the pin low on rese t, an external 10 k ? pull- down resistor should be c onnected. once the pin state is latched following reset, the gpio[4:6] pins funtion without affecting pll operation. 6.3 synchronous clocking to guarantee synchronous measurements through- out a sensor network, a sy stem clock should be dis- tributed to arrive at all nodes in phase. the distributed system clock can either be the full 32.768 mhz master clock, or the cs5378 pll can create a synchronous 32.768 mhz clock from a slower clock. to ensure the generated clock re- mains synchronous with the network, the cs5378 pll uses a phase/frequenc y detector architecture. pll clk dspcfg register mclk internal clocks figure 12. clock generation block diagram clock divider generator and mclk output pll[2:0] 32.768 mhz pll[2:0] pll mode 111 32.768 mhz clock input (pll bypass). 110 1.024 mhz clock input. 101 2.048 mhz clock input. 100 4.096 mhz clock input. 011 32.768 mhz clock input (pll bypass). 010 1.024 mhz manchester input. 001 2.048 mhz manchester input. 000 4.096 mhz manchester input. table 5. pll mode selections
cs5378 ds639f1 23 6.4 master clock jitter and skew care must be taken to mi nimize jitter and skew on the distributed system cloc k as both parameters af- fect measurement performance. jitter on the input clock causes jitter in the generat- ed modulator clock, result ing in sample timing er- rors and increased noise. skew between input clocks from node to node cre- ates a sample timing offset , resulting in systematic measurement errors in a reconstructed signal.
cs5378 ds639f1 24 7. synchronization the cs5378 has a dedicated sync input that aligns the internal digita l filter phase and generates an external signal for s ynchronizing modulator an- alog sampling. by providing simultaneous rising edges to the sync pins of multiple cs5378 devic- es, synchronous sampling across a network can be guaranteed. 7.1 pin description sync - pin 19 synchronization input, rising edge triggered. 7.2 msync generation the sync signal ri sing edge is used to generate a retimed synchronization signal, msync. the msync signal reinitializes internal digital filter phase and is driven ont o the msync output pin to phase align modulator analog sampling. the msen bit in the digital filter config register (0x00) enables msync generation. see ?modula- tor interface? on page 36 for more information about msync. 7.3 digital filter synchronization the internal msync signal resets the digital filter state machine to establ ish a known digital filter phase. filter convolutions restart, and the next out- put word is available one full sample period later. repetitive synchroniza tion is supported when sync events occur at exactly the selected output rate. in this case, re-s ynchronization will occur at the start of a convolution cycle when the digital fil- ter state machine is already reset. 7.4 modulator synchronization the external msync signal phase aligns modula- tor analog sampling when connected to the cs5371 msync input. this ensures synchronous analog sampling relative to mclk. repetitive synchronizatio n of the modulators is supported when sync events occur at exactly the selected output rate. in this case, re-synchroniza- tion always occurs at the start of analog sampling. 7.5 test bit stream synchronization when the test bit stream generator is enabled, an msync signal can reset th e internal data pointer. this restarts the test bit stream from the first data point to establish a known output signal phase. the tsync bit in the digi tal filter tbscfg regis- ter (0x2a) enables synchroni zation of the test bit stream by msync. when tsync is disabled, the test bit stream phase is not affected by msync. figure 13. synchronization block diagram sync msync digital filter generator msync 0 1 msen 0 1 tsync test bit stream output
cs5378 ds639f1 25 8. configuration by eeprom after reset, the cs5378 re ads the state of the gpio7:boot pin to determine a source for con- figuration commands. if boot is high, the cs5378 initiates serial transa ctions to read config- uration information from an external eeprom. 8.1 pin descriptions pins required for eeprom boot are listed here, other serial pins are inactive. sck - pin 24 serial clock output, nominally 1.024 mhz. miso - pin 25 serial data input pin. va lid on rising edge of sck, transition on falling edge. mosi - pin 26 serial data output pin. valid on rising edge of sck, transition on falling edge. ss:eecs - pin 27 eeprom chip select output, active low. 8.2 eeprom hardware interface when booting from eeprom the cs5378 actively performs serial transacti ons, as shown in figure 15, to read configur ation commands and data. 8-bit spi opcodes and 16-bit addresses are combined to read back 8-bit configur ation commands and 24-bit configuration data. system design should incl ude a connection to the configuration eeprom for in-circuit reprogram- ming. the cs5378 serial pi ns tri-state when inac- tive to support external connections to the serial bus. 8.3 eeprom organization the boot eeprom holds th e 8-bit commands and 24-bit data required to initialize the cs5378 into an operational state. configur ation information starts at memory location 0x10, with addresses 0x00 to 0x0f free for use as manuf acturing header informa- tion. the first serial transact ion reads a 1-byte command from memory location 0x10 and then, depending on the command type, reads multiple 3-byte data words to complete the command. command and data reads continue until the ?filter start? command is recognized. ss:eecs sck miso mosi cs5378 at25640 cs sck si so 27 24 25 26 1 6 2 5 vd gnd wp vcc hold 387 4 figure 14. eeprom configuration block diagram
cs5378 ds639f1 26 sck mosi ss:eecs msb lsb miso x 61 2 3 4 5 msb lsb 61 2 3 4 5 18 27 6 5 4 3 cycle mosi miso 0x03 addr data1 data3 data2 ss:eecs read 1 byte / 3 byte addr cmd addr data 2 byte figure 15. eeprom seri al read transactions serial read from eeprom instruction opcode address definition read 0x03 addr[15:0] read data beginning at the address given in addr.
cs5378 ds639f1 27 the maximum number of bytes that will be written for a single configuration is less than 2 kbyte (16 kbit), including command overhead: supported serial confi guration eeproms are spi mode 0 (0,0) compatible, 16-bit addresses, 8- bit data, larger than 2 kbyte (16 kbit). atmel at25640, at25128, or similar serial eeproms are recommended. 8.4 eeprom configuration commands a summary of availabl e eeprom commands is shown in table 7. write df register - 0x01 this eeprom command writes a data value to the specified digital filter register. digital filter regis- ters control hardware pe ripherals and filtering functions. see ?digital filt er registers? on page 71 for the bit definitions of th e digital filter registers. sample command: write digital filter regi ster 0x00 with data value 0x060431. then write 0x20 with data 0x000240. 01 00 00 00 06 04 31 01 00 00 20 00 02 40 write fir coefficients - 0x02 this eeprom command wr ites custom coeffi- cients for the fir1 and fi r2 filters. the first two data words set the number of fir1 and fir2 coef- ficients to be written. the remaining data words are the concatenated fir1 and fir2 coefficients. a maximum of 255 coefficien ts can be written for each fir filter, though the available digital filter computation cycles will limit their practical size. see ?fir filter? on page 44 for more information about fir filter coefficients. sample command: write fir1 coeffici ents 0x00022e, 0x000771 then fir2 coefficients 0xffffb9, 0xfffe8d. 02 00 00 02 00 00 02 00 02 2e 00 07 71 ff ff b9 ff fe 8d write iir coefficients - 0x03 this eeprom command wr ites custom coeffi- cients for the two stage ii r filter. the iir architec- ture and number of coeffi cients is fixed, so eight data words containing coefficient values always immediately follow the co mmand byte. the iir co- efficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. see ?iir filter? on page 52 for more information about ii r filter coefficients. figure 16. 8 kbyte eeprom memory organization 0000h 1fffh eeprom manufacturing information eeprom command and data values mfg header 8-bit command 0010h n x 24-bit data 8-bit command n x 24-bit data . . . table 6. maximum eeprom configuration memory requirement bytes digital filter registers (12) 84 fir coefficients (255+255) 1537 iir coefficients (3+5) 25 ?filter start? command 1 total bytes 1647
cs5378 ds639f1 28 sample command: write iir1 coefficients 0x84bc9d, 0x7da1b1, 0x825e4f, and iir2 coefficients 0x83694f, 0x3cad5f, 0x3e5104, 0x835df8, 0x3e5104. 03 84 bc 9d 7d a1 b1 82 5e 4f 83 69 4f 3c ad 5f 3e 51 04 83 5d f8 3e 51 04 write rom coefficients - 0x04 this eeprom command selects the on-chip coef- ficients for the fir1, fi r2, iir 1st order, and iir 2nd order filters for use by the digital filter. one data word is required to select which internal coef- ficient sets to use. see ?filter coefficient selec- tion? on page 38 for inform ation about selecting on-chip fir and iir coefficient sets. sample command: select iir1 and iir2 3 hz @ 500 sps low-cut co- efficients, with fir1 a nd fir2 linear phase high- cut coefficients. data word 0x002200. 04 00 22 00 filter start - 0x07 this eeprom command initializes and starts the digital filter. measuremen t data becomes available one full sample period after this command is is- sued. no data words ar e required for this ee- prom command. sample command: 07 table 7. eeprom boot configuration commands (data) indicates multiple words of this type are to be written. name cmd 8-bit data 24-bit description nop 00 - no operation write df register 01 reg data write digital filter register write fir coefficients 02 num fir1 num fir2 (fir coef) write custom fir coefficients write iir coefficients 03 a11 b10 b11 a21 a22 b20 b21 b22 write custom iir coefficients write rom coefficients 04 coef sel use on-chip coefficients nop 05 - no operation nop 06 - no operation filter start 07 - start digital filter operation
cs5378 ds639f1 29 8.5 example eeprom configuration table 8 shows an exampl e eeprom file for a min- imal cs5378 configuration. table 8. example eeprom file addr data description 00 00 mfg header 01 00 02 00 03 00 04 00 05 00 06 00 07 00 08 00 09 00 0a 00 0b 00 0c 00 0d 00 0e 00 0f 00 10 04 write rom coefficients 11 00 12 22 13 00 14 01 write config register 15 00 16 00 17 00 18 06 19 04 1a 31 1b 01 write filtcfg register 1c 00 1d 00 1e 20 1f 00 addr data description 21 02 22 40 23 01 write tbscfg register 24 00 25 00 26 2a 27 07 28 40 29 40 2a 01 write tbsgain register 2b 00 2c 00 2d 2b 2e 04 2f b0 30 00 31 07 filter start
cs5378 ds639f1 30 9. configuration by microcontroller after reset, the cs5378 re ads the state of the gpio7:boot pin to determine a source for con- figuration commands. if boot is low, the cs5378 receives configuration co mmands from a micro- controller. 9.1 pin descriptions pins required for microc ontroller boot are listed here, other serial pins are inactive. ss:eecs - pin 27 slave select input pin, active low. serial chip select input from a microcontroller. mosi - pin 26 serial data input pin. va lid on rising edge of sck, transition on falling edge. miso - pin 25 serial data output pin. valid on rising edge of sck, transition on falling edge. open drain output requiring a 10 k ? pull-up resistor. sck - pin 24 serial clock input pin. se rial clock i nput from mi- crocontroller, maximum 4.096 mhz. 9.2 microcontroller hardware interface when booting from a microcontroller the cs5378 receives configuration co mmands and configura- tion data through se rial transactions, as shown in figure 18. 8-bit spi opcode s and 8-bit addresses are combined to read and write 24-bit configuration commands and data. microcontroller serial tran sactions require toggling the ss:eecs pin as the cs5378 chip select and writing a serial clock to the sck input. serial data is input to the cs5378 on the mosi pin, and output on the miso pin. 9.3 microcontroller serial transactions microcontroller configur ation commands are writ- ten to the digital filter th rough spi registers. a 24- bit command and two 24- bit data words can be written to the spi regist ers in any single serial transaction. some comma nds require additional data words through additiona l serial transactions to complete. 9.3.1 spi opcodes a microcontroller communicates with the cs5378 serial port using standard 8-bit spi opcodes and an 8-bit address. the standa rd spi ?read? and ?write? opcodes are listed in figure 18. sck miso mosi pin logic spi figure 17. serial interface block diagram command ss:eecs registers digital filter interpreter serial
cs5378 ds639f1 31 sck mosi figure 18. microcontroller serial transactions ss:eecs msb lsb miso x 61 2 3 4 5 msb lsb 61 2 3 4 5 18 27 6 5 4 3 cycle miso 0x02 addr data1 mosi miso mosi microcontroller write to spi registers microcontroller read from spi registers datan data2 ss:eecs ss:eecs 0x03 addr data1 datan data2 instruction opcode address definition write 0x02 addr[7:0] write spi registers beginning at the address in addr. read 0x03 addr[7:0] read spi register s beginning at the address in addr.
cs5378 ds639f1 32 9.3.2 spi registers the spi registers are shown in figure 19 and are 24-bit registers mapped into an 8-bit register space as high, mid, and low bytes. see ?spi registers? on page 66 for the bit definiti ons of the spi registers. 9.3.3 serial transactions a serial transaction to th e spi registers starts with an spi opcode, followed by an address, and then some number of data bytes written or read starting at that address. typical serial write transactions require sending groups of 5, 8, or 11 tota l bytes to the spicmd or spidat1 registers: 5-byte write to spicmd 02 03 12 34 56 5-byte write to spidat1 02 06 12 34 56 8-byte write to spicmd, spidat1 02 03 12 34 56 ab cd ef 8-byte write to spidat1, spidat2 02 06 12 34 56 ab cd ef 11-byte write to spicmd, spidat1, spidat2 02 03 12 34 56 ab cd ef 65 43 21 typical serial read trans actions require groups of 3 or 5 bytes, split between writing into mosi and reading from miso. 3-byte read of mid-byte of spictrl mosi: 03 01 00 miso: xx xx 12 5-byte read of spidat1 mosi: 03 06 00 00 00 miso: xx xx 12 34 56 9.3.4 multiple serial transactions some configuration comma nds require multiple se- rial transactions to comp lete. there must be a small delay between tran sactions for the cs5378 to process the incoming data. two methods can be used to ensure the cs5378 is ready to receive the next configuration command. 1) delay a fixed 1 ms pe riod to guarantee enough time for the command to be completed. 2) verify the status of the e2dreq bit by reading the spictrl register. wh en low, the cs5378 is ready for the next command. 9.3.5 polling e2dreq one transaction type that can always be performed no matter the delay from th e previous configuration command is reading e2dreq in the mid-byte of the spictrl register. a 3-byte read transaction. mosi: 03 01 00 miso: xx xx 01 <- e2dreq bit high miso: xx xx 00 <- e2dreq bit low the e2dreq bit reads high while a serial transac- tion is being processed. when low, the digital filter is ready to receive a new serial transaction. name addr. type # bits description spictrl 00 - 02 r/w 8, 8, 8 spi control spicmd 03 - 05 r/w 8, 8, 8 spi command spidat1 06 - 08 r/w 8, 8, 8 spi data 1 spidat2 09 - 0b r/w 8, 8, 8 spi data 2 figure 19. spi registers
cs5378 ds639f1 33 9.4 microcontroller configuration commands a summary of available mi crocontroller configura- tion commands is listed in table 9. write df register - 0x01 this configuration co mmand writes a specified digital filter register. dig ital filter registers control hardware peripherals and filtering functions. see ?digital filter registers? on page 71 for the bit def- initions of the digital filter registers. sample command: write digital filter regi ster 0x00 with data value 0x060431. then write 0x20 with data 0x000240. 02 03 00 00 01 00 00 00 06 04 31 delay 1 ms or poll e2dreq 02 03 00 00 01 00 00 20 00 02 40 delay 1 ms or poll e2dreq read df register - 0x02 this command reads a specifi ed digital filter regis- ter. the register value is requested in the first serial transaction, with the re gister value copied to spidat1 and read in a subs equent serial transac- tion. sample command: read digital filter registers 0x00 and 0x20. 02 03 00 00 02 00 00 00 delay 1 ms or poll e2dreq mosi: 03 06 00 00 00 miso: xx xx 06 04 31 02 03 00 00 02 00 00 20 delay 1 ms or poll e2dreq mosi: 03 06 00 00 00 miso: xx xx 00 02 40 [data] indicates data word returned fr om digital filter. (data) indicates multiple words of this type are to be written. name cmd 24-bit dat1 24-bit dat2 24-bit description nop 000000 - - no operation write df register 000001 reg data write digital filter register read df register 000002 reg [data] - - read digital filter register write fir coefficients 000003 num fir1 (fir coef) num fir2 (fir coef) write custom fir coefficients write iir coefficients 000004 a11 b11 a22 b21 b10 a21 b20 b22 write custom iir coefficients write rom coefficients 000005 coef sel - use on-chip coefficients nop 000006 - - no operation nop 000007 - - no operation filter start 000008 - - start digital filter operation filter stop 000009 - - stop digital filter operation table 9. microcontroller bo ot configuration commands
cs5378 ds639f1 34 write fir coefficients - 0x03 this command writes cust om coefficients for the fir1 and fir2 filters. the first two data words set the number of fir1 and fi r2 coefficients to be written. the remaining data words are the concate- nated fir1 and fi r2 coefficients. a maximum of 255 coefficien ts can be written for each fir filter, though the available digital filter computation cycles will limit their practical size. see ?fir filter? on page 44 for more information about fir filter coefficients. sample command: write fir1 coefficients 0x00022e, 0x000771 then fir2 coefficients 0xffffb9, 0xfffe8d. 02 03 00 00 03 00 00 02 00 00 02 delay 1 ms or poll e2dreq 02 06 00 02 2e 00 07 71 delay 1 ms or poll e2dreq 02 06 ff ff b9 ff fe 8d delay 1 ms or poll e2dreq write iir coefficients - 0x04 this command writes cust om coefficients for the two stage iir filter. the iir architecture and num- ber of coefficients is fixe d, so eight coefficient val- ues immediately follow this command. the iir coefficient write order is: a11, b10, b11, a21, a22, b20, b21, and b22. see ?iir filter? on page 52 for more information about ii r filter coefficients. sample command: write iir1 coefficients 0x84bc9d, 0x7da1b1, 0x825e4f, and iir2 coefficients 0x83694f, 0x3cad5f, 0x3e5104, 0x835df8, 0x3e5104. 02 03 00 00 04 84 bc 9d 7d a1 b1 delay 1 ms or poll e2dreq 02 06 82 5e 4f 83 69 4f delay 1 ms or poll e2dreq 02 06 3c ad 5f 3e 51 04 delay 1 ms or poll e2dreq 02 06 83 5d f8 3e 51 04 delay 1 ms or poll e2dreq write rom coefficients - 0x05 this configuration comm and selects the on-chip coefficients for fir1, fir 2, iir 1st order, and iir 2nd order filters for use by the digital filter. one data word is required to select which internal coef- ficient sets to use. see ?filter coefficient selec- tion? on page 38 for inform ation about selecting on-chip fir and iir coefficient sets. sample command: select iir1 and iir2 3 hz @ 500 sps low-cut co- efficients, with fir1 a nd fir2 linear phase high- cut coefficients. data word 0x002200. 02 03 00 00 05 00 22 00 delay 1 ms or poll e2dreq filter start - 0x08 this command initializes and starts the digital fil- ter. measurement data becomes available one full sample period after this command is issued. no data words are required for this command. sample command: 02 03 00 00 08 delay 1 ms or poll e2dreq filter stop - 0x09 this command disables the digital filter. measure- ment data output stops immediately after this com- mand is issued. no data words are required for this command. sample command: 02 03 00 00 09 delay 1 ms or poll e2dreq
cs5378 ds639f1 35 9.5 example microcontroller configuration table 10 shows an example microcontroller tran sactions for a minimal cs5378 configuration. table 10. example microcontroller configuration transaction spi data description 01 02 03 00 00 05 00 22 00 write rom coefficients 02 delay 1ms or poll e2dreq 03 02 03 00 00 01 00 00 00 06 04 31 write config register 04 delay 1ms or poll e2dreq 05 02 03 00 00 01 00 00 20 00 02 40 write filtcfg register 06 delay 1ms or poll e2dreq 07 02 03 00 00 01 00 00 2a 07 40 40 write tbscfg register 08 delay 1ms or poll e2dreq 09 02 03 00 00 01 00 00 2b 04 b0 00 write tbsgain register 10 delay 1ms or poll e2dreq 11 02 03 00 00 08 filter start
cs5378 ds639f1 36 10. modulator interface the cs5378 performs di gital filtering for a ? type modulator. signals from the ? modulators are connected through the modul ator data interface (mdi). 10.1 pin descriptions mclk - pin 11 modulator clock output . nominally 2.048 mhz or 1.024 mhz. msync - pin 12 modulator synchronizati on signal output. generat- ed from the sync input. mdata - pin 13 modulator data input , nominally 512 kbit/s. mflag - pin 14 modulator flag input. driven high when the mod- ulator is unstable due to an analog over-range con- dition. 10.2 modulator clock generation the mclk output is a lo w-jitter, low-skew modu- lator clock generated from the 32.768 mhz master clock. mclk typically operates at 2.048 mhz unless an- alog low-power modes require a 1.024 mhz mod- ulator clock. the mclk rate is selected and the mclk output is enabled by bits in the digital filter config reg- ister (0x00). by default mclk is disabled and driven low. 10.3 modulator synchronization the msync output signal follows an input to the sync pin. msync phase aligns the modulator sampling instant to guarantee synchronous analog sampling across a me asurement network. msync is enabled by a bi t in the config register (0x00). by default sync inputs do not cause an msync output. figure 20. modulator data interface fir iir filters filter output to high speed serial interface dc offset correction output rate 4000 sps ~ 1 sps & gain mdata mflag mdi input 512 khz mclk / generate msync clk sync msync sinc filter mclk
cs5378 ds639f1 37 10.4 modulator data input the mdata input expects 1-bit ? data at a 512 khz or 256 khz rate. the input rate is selected by a bit in the config register (0x00). by default, mdata is expected at 512 khz. the mdata input one?s de nsity is designed for full scale positive at 86% and full scale negative at 14%, with absolute maxi mum over-range capabili- ty to 93% and 7%. these raw ? inputs are deci- mated and filtered by the di gital filter to create 24- bit samples at the output rate. 10.5 modulator flag input a high mflag input signal indicates the ? mod- ulator has become unstabl e due to an analog over- range input signal. on ce the over-range signal is reduced, the modulator rec overs stability and the mflag signal is cleared. the mflag input is mapped to a status bit in the serial data output stream , and is associated with each sample when written. see ?serial data inter- face? on page 58 for more information on the mflag error bit in the serial data status byte.
cs5378 ds639f1 38 11. digital filter initialization the cs5378 digital filter c onsists of three multi- stage sections: a three stag e sinc filter, a two stage fir filter, and a two stage iir filter. to initialize the digital filter, fir and iir coeffi- cient sets are selected using configuration com- mands, and the filtcfg regi ster (0x20) is written to select the output filt er stage, the output word rate, and the number of en abled channels. the dig- ital filter clock rate is then selected by writing the config register (0x00). 11.1 filter coefficient selection selection of sinc filter co efficients is not required as they are selected auto matically based on the pro- grammed output word rate. digital filter fir and iir coefficients are selected using the ?write fir coef ficients? and ?write iir coefficients?, or the ?write rom coefficients? configuration commands. when writing the fir and iir coefficients from rom, a data word selects an on-chip coefficient set fo r each filter stage. fig- ure 22 shows the format of the coefficient selection word, and the available coefficient sets for each se- lection. characteristics of the on-chip digital filter coeffi- cients are discussed in th e ?sinc filter?, ?fir fil- ter?, and ?iir filter? sect ions of this data sheet. 11.2 filter configuration options digital filter parameters ar e selected by bits in the filtcfg register (0x20), and the digital filter clock rate is selected by bits in the config regis- ter (0x00). 11.2.1 output filter stage the digital filter can out put data following any stage in the filter chain. the output filter stage is selected by the fsel bits in the filtcfg register. taking data from the sinc or fir1 filter stages re- duces the overall decimation of the filter chain and increases the output rate, as discussed in the next section. taking data from fir2, iir1, iir2, or iir3 results in data at the selected rate. figure 21. digital filter stages sinc filter 2 - 64000 fir1 4 fir2 2 iir1 iir2 1st order 2nd order output to high speed serial data interface dc offset correction output rate 4000 sps ~ 1 sps & gain modulator 512 khz input
cs5378 ds639f1 39 11.2.2 output word rate the cs5378 digital filter supports output word rates (owrs) between 4000 sps and 1 sps. the output word rate is select ed by the dec bits in the filtcfg register. when taking data directly from the sinc filter, the decimation of the fir1 and fir2 stages is by- passed and the actual output word rate is multiplied by a factor of eight compar ed with the register se- lection. when taking data directly from fir1, the decimation of the fir2 stage is bypassed and the actual output word rate is multiplied by a factor of two. data taken from the fir2, iir1, iir2, or iir3 filtering stages is output at the selected rate. 11.2.3 digital filter clock the digital filter clock ra te is programmable be- tween 8.192 mhz and 32 khz by bits in the con- fig register. computation cycles the minimum digital filter clock rate for a config- uration depends on the co mputation cycles required to complete digital filter convolutions at the select- ed output word rate. all configurations work for a maximum digital filter cl ock, but lower clock rates consume less power. standby mode the cs5378 can be placed in a low-power standby mode by sending the ?filte r stop? configuration command and programming th e digital filter clock to 32 khz. in this mode th e digital filter idles, con- suming minimal power until re-enabled by later configuration commands. bits 23:20 19:16 15:12 11:8 7:4 3:0 selection 0000 0000 iir2 iir1 fir2 fir1 figure 22. fir and iir coef ficient set selection word bits 15:12 iir2 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3hz @ 500sps 0011 3hz @ 333sps 0100 3hz @ 250sps bits 11:8 iir1 coefficients 0000 3 hz @ 2000 sps 0001 3 hz @ 1000 sps 0010 3 hz @ 500 sps 0011 3 hz @ 333 sps 0100 3 hz @ 250 sps bits 7:4 fir2 coefficients 0000 linear phase 0001 minimum phase bits 3:0 fir1 coefficients 0000 linear phase 0001 minimum phase
cs5378 ds639f1 40 12. sinc filter the sinc filter primary pur pose is to attenuate out- of-band noise components from the ? modula- tors. while doing so, they decimate 1-bit ? data into lower frequency 24-bit data suitable for the fir and iir filters. the sinc filter has thre e cascaded sections, sinc1, sinc2, and sinc3, which are each made up of the smaller stages shown in figure 23. the selected output word rate in the filtcfg reg- ister automatically determines the coefficients and decimation ratios selected for the sinc filters. 12.1 sinc1 filter the first section is sinc 1, a single stage 5th order fixed decimate by 8 sinc filter. this sinc filter decimates the incoming 1-bit ? bit stream from the modulators down to a 64 khz rate. 12.2 sinc2 filter the second section is sinc 2, a multi-stage, vari- able order, variable d ecimation sinc filter. de- pending on the selected output word rate in the filtcfg register, differen t cascaded sinc2 stag- es are enabled, as shown in table 11. 12.3 sinc3 filter the last section is sinc3, a flexible multi-stage variable order, variable decimation sinc filter. depending on the selected output word rate in the filtcfg register, differen t sinc3 stages are en- abled, as shown in table 11. 12.4 sinc filter synchronization the sinc filter is synchronized to the external sys- tem by the msync signal, which is generated from the sync input. th e msync signal sets a reference time (time 0) for all filter operations, and the sinc filter is restarte d to phase align with this reference time. sinc1 8 5th order 4th order figure 23. sinc filter block diagram 1-bit 24-bit ?? 2 stage1 sinc2 4th order 2 stage2 sinc2 5th order 2 stage3 sinc2 6th order 2 stage4 sinc2 4th order 5 stage1 sinc3 4th order 5 stage2 sinc3 4th order 5 stage3 sinc3 5th order 2 stage5 sinc3 6th order 3 stage6 sinc3 6th order 2 stage7 sinc3 output input 5th order 5 stage4 sinc3
cs5378 ds639f1 41 figure 24. sinc filter stages sinc1 ? single stage, fixed decimate by 8 5 th order decimate by 8, 36 coefficients sinc2 ? multi-stage, variable decimation stage 1: 4 th order decimate by 2, 5 coefficients stage 2: 4 th order decimate by 2, 5 coefficients stage 3: 5 th order decimate by 2, 6 coefficients stage 4: 6 th order decimate by 2, 7 coefficients sinc3 ? multi-stage, variable decimation stage 1: 4 th order decimate by 5, 17 coefficients stage 2: 4 th order decimate by 5, 17 coefficients stage 3: 4 th order decimate by 5, 17 coefficients stage 4: 5 th order decimate by 5, 21 coefficients stage 5: 5 th order decimate by 2, 6 coefficients stage 6: 6 th order decimate by 3, 13 coefficients stage 7: 6 th order decimate by 2, 7 coefficients table 11. sinc filter configurations sinc filters fir2 output word rate dec bit setting sinc1 deci- mation sinc2 deci- mation sinc2 stages sinc3 deci- mation sinc3 stages 4000 0111 8 2 4 - - 2000 0110 8 4 3,4 - - 1000 0101 8 8 2,3,4 - - 500 0100 8 16 1,2,3,4 - - 333 0011 8 8 2,3,4 3 6 250 0010 8 16 1,2,3,4 2 7 200 0001 8 4 3,4 10 4,7 125 0000 8 16 1,2,3,4 4 5,7 100 1111 8 4 3,4 20 3,5,7 50 1110 8 8 2,3,4 20 3,5,7 40 1101 8 4 3,4 50 3,4,7 25 1100 8 16 1,2,3,4 20 3,5,7 20 1011 8 4 3,4 100 2,3,5,7 10 1010 8 8 2,3,4 100 2,3,5,7 5 1001 8 16 1,2,3,4 100 2,3,5,7 1 1000 8 16 1,2,3,4 500 1,2,3,5,7
cs5378 ds639f1 42 filter type system function filter coefficients sinc2 (stage 1) sinc2 (stage 2) 4 th order decimate by 2 5 coefficients 4 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 4 h 2 = 6 h 3 = 4 h 4 = 1 sinc2 (stage 3) 5 th order decimate by 2 6 coefficients 5 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 5 h 2 = 10 h 3 = 10 h 4 = 5 h 5 = 1 sinc2 (stage 4) 6 th order decimate by 2 7 coefficients 6 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 6 h 2 = 15 h 3 = 20 h 4 = 15 h 5 = 6 h 6 = 1 filter type system function filter coefficients sinc1 5 th order decimate by 8 36 coefficients 5 1 8 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 18 = 2460 h 1 = 5 h 19 = 2380 h 2 = 15 h 20 = 2226 h 3 = 35 h 21 = 2010 h 4 = 70 h 22 = 1750 h 5 = 126 h 23 = 1470 h 6 = 210 h 24 = 1190 h 7 = 330 h 25 = 926 h 8 = 490 h 26 = 690 h 9 = 690 h 27 = 490 h 10 = 926 h 28 = 330 h 11 = 1190 h 29 = 210 h 12 = 1470 h 30 = 126 h 13 = 1750 h 31 = 70 h 14 = 2010 h 32 = 35 h 15 = 2226 h 33 = 15 h 16 = 2380 h 34 = 5 h 17 = 2460 h 35 = 1 table 12. sinc1 and si nc2 filter coefficients
cs5378 ds639f1 43 table 13. sinc3 filter coefficients filter type system function filter coefficients sinc3 (stage 1) sinc3 (stage 2) sinc3 (stage 3) 4 th order decimate by 5 17 coefficients 4 1 5 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 9 = 80 h 1 = 4 h 10 = 68 h 2 = 10 h 11 = 52 h 3 = 20 h 12 = 35 h 4 = 35 h 13 = 20 h 5 = 52 h 14 = 10 h 6 = 68 h 15 = 4 h 7 = 80 h 16 = 1 h 8 = 85 sinc3 (stage 4) 5 th order decimate by 5 21 coefficients 5 1 5 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 11 = 365 h 1 = 5 h 12 = 320 h 2 = 15 h 13 = 255 h 3 = 35 h 14 = 185 h 4 = 70 h 15 = 121 h 5 = 121 h 16 = 70 h 6 = 185 h 17 = 35 h 7 = 255 h 18 = 15 h 8 = 320 h 19 = 5 h 9 = 365 h 20 = 1 h 10 = 381 sinc3 (stage 5) 5 th order decimate by 2 6 coefficients 5 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 5 h 2 = 10 h 3 = 10 h 4 = 5 h 5 = 1 sinc3 (stage 6) 6 th order decimate by 3 13 coefficients 6 1 3 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 7 = 126 h 1 = 6 h 8 = 90 h 2 = 21 h 9 = 50 h 3 = 50 h 10 = 21 h 4 = 90 h 11 = 6 h 5 = 126 h 12 = 1 h 6 = 141 sinc3 (stage 7) 6 th order decimate by 2 7 coefficients 6 1 2 1 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? z z z h h 0 = 1 h 1 = 6 h 2 = 15 h 3 = 20 h 4 = 15 h 5 = 6 h 6 = 1
cs5378 ds639f1 44 13. fir filter the finite impulse respons e (fir) filter block con- sists of two cascaded stages, fir1 and fir2. it compensates for sinc fi lter droop and creates a low-pass corner to block aliased components of the input signal. on-chip linear phase or minimum phase coeffi- cients can be selected using a configuration com- mand, or the coefficients can be programmed for a custom filter response. 13.1 fir1 filter the fir1 filter stage has a decimate by four archi- tecture. it compensates for sinc filter droop and flattens the magnitude re sponse of the pass band. the on-chip linear and minimum phase coefficient sets are 48-tap, with a maximum 255 programma- ble coefficients. all coef ficients are normalized to 24-bit two?s complement full scale, 0x7fffff. the characteristic equati on for fir1 is a convolu- tion of the input values, x( n), and the filter coeffi- cients, h(k), to produce an output value, y. y = [h(k)*x(n-k)] + [h(k+1)*x(n-(k+1))] + ... 13.2 fir2 filter the fir2 filter stage ha s a decimate by two archi- tecture. it creates a lo w-pass brick wall filter to block aliased components of the input signal. the on-chip linear and min imum phase coefficient sets are 126-tap, with a maximum 255 programma- ble coefficients. all coefficients are normalized to 24-bit two?s complement full scale, 0x7fffff. the characteristic equati on for fir2 is a convolu- tion of the input values, x( n), and the fi lter coeffi- cients, h(k), to produce an output value, y. y = [h(k)*x(n-k)] + [h(k+1)*x(n-(k+1))] + ... 13.3 on-chip fir coefficients two sets of on-chip coeffi cients, linear phase and minimum phase, are available for fir1 and fir2. performance of the on-chip coefficient sets is very good, with excellent rippl e and stop band charac- teristics as described in figure 26 and table 14. which on-chip coefficient se t to use is selected by a data word following the ?write rom coeffi- cients? configuration comm and. see ?filter coef- ficient selection? on pa ge 38 for information about selecting on-chip coefficient sets. fir1 filter - decimate by 4 fir2 filter - decimate by 2 figure 25. fir filter block diagram
cs5378 ds639f1 45 13.4 programmable fir coefficients a maximum of 255 + 255 coef ficients can be pro- grammed into fir1 and fi r2 to create a custom filter response. the total number of coefficients for the fir filter is fundament ally limited by the avail- able computation cycles in the digital filter, which itself is determined by th e digital filter clock rate. custom filter sets s hould normalize the maximum coefficient value to 24-bi t two?s complement full scale, 0x7fffff, and scal e all other coefficients accordingly. to maintain maximum internal dy- namic range, the cs5378 fir filter performs dou- ble precision calculations with an automatic gain correction to scal e the final output. custom fir coefficients are uploaded using the ?write fir coefficients ? configuration command. see ?eeprom configuration commands? on page 27 or ?microcontroll er configuration com- mands? on page 33 for information about writing custom fir coefficients. 13.5 fir filter synchronization the fir1 and fir2 filter s are synchronized to the external system by the msync signal, which is generated from the sync input. the msync sig- nal sets a reference time (t ime 0) for all filter oper- ations, and the fir filter s are restarted to phase align with this reference time.
cs5378 ds639f1 46 fir1 ? single stage, fixed decimate by 4 coefficient set 0: linear phase decimate by 4, 48 coefficients coefficient set 1: minimum phase decimate by 4, 48 coefficients sinc droop compensation filter fir2 ? single stage, fixed decimate by 2 coefficient set 0: linear phase decimate by 2, 126 coefficients coefficient set 1: minimum phase decimate by 2, 126 coefficients brick wall low-pass filter, flat to 40% f s combined sinc + fir digital filter specifications passband ripple less than +/- 0.01 db below 40% f s transition band -3 db frequency at 42.89% f s stopband attenuation greater than 130 db above 50% f s figure 26. fir filter stages sinc + fir filters fir2 output word rate sinc deci- mation fir1 deci- mation fir2 deci- mation total deci- mation passband ripple ( db) stopband atten- uation (db) 4000 16 4 2 128 0.0042 130.38 2000 32 4 2 256 0.0045 130.38 1000 64 4 2 512 0.0040 130.42 500 128 4 2 1024 0.0041 130.42 333 192 4 2 1536 0.0080 130.45 250 256 4 2 2048 0.0064 130.43 200 320 4 2 2560 0.0043 130.44 125 512 4 2 4096 0.0046 130.42 100 640 4 2 5120 0.0040 130.43 50 1280 4 2 10240 0.0040 130.43 40 1600 4 2 12800 0.0040 130.44 25 2560 4 2 20480 0.0040 132.98 20 3200 4 2 25600 0.0036 130.43 10 6400 4 2 51200 0.0036 130.43 5 12800 4 2 102400 0.0036 130.43 1 64000 4 2 512000 0.0029 134.31 table 14. fir filter characteristics
cs5378 ds639f1 47 table 15. sinc + fir group delay individual filter stage group delay (no iir) decimation ratios number of coefficients group delay (input rate) sinc1 8 36 17.5 sinc2 stage 4 2 7 3.0 stages 3,4 2,2 6,7 8.5 stages 2,3,4 2,2,2 5,6,7 19.0 stages 1,2,3,4 2,2,2,2 5,5,6,7 40.0 sinc3 stage 7 2 7 3.0 stage 6 3 13 6.0 stages 5,7 2,2 6,7 8.5 stages 4,7 5,2 21,7 25.0 stages 3,5,7 5,2,2 17,6,7 50.5 stages 3,4,7 5,5,2 17,21,7 133.0 stages 2,3,5,7 5,5,2,2 17,17,6,7 260.5 stages 1,2,3,5,7 5,5,5,2,2 17,17,17,6,7 1310.5 fir1 coefficient set 0 4 48 23.5 coefficient set 1 4 48 see figure fir2 coefficient set 0 2 126 62.5 coefficient set 1 2 126 see figure cumulative linear phase group delay (no iir) fir2 output word rate sinc output group delay (sinc filter input rate) fir1 output group delay (sinc filter input rate) fir2 output group delay (sinc filter input rate) fir2 output group delay (fir2 output word rate) 4000 41.5 417.5 4417.5 34.5117 2000 85.5 837.5 8837.5 34.5215 1000 169.5 1673.5 17673.5 34.5186 500 337.5 3345.5 35345.5 34.5171 333 553.5 5065.5 53065.5 34.5479 250 721.5 6737.5 70737.5 34.5398 200 885.5 8405.5 88405.5 34.5334 125 1425.5 13457.5 141457.5 34.5355 100 1701.5 16741.5 176741.5 34.5198 50 3401.5 33481.5 353481.5 34.5197 40 4341.5 41941.5 441941.5 34.5267 25 6801.5 66961.5 706961.5 34.5196 20 8421.5 83621.5 883621.5 34.5165 10 16841.5 167241.5 1767241.5 34.5164 5 33681.5 334481.5 3534481.5 34.5164 1 168081.5 1672081.5 17672081.5 34.5158
cs5378 ds639f1 48 minimum phase group delay fir1 minimum phase group delay (normalized frequency) fir2 minimum phase group delay (normalized frequency) table 16. minimum phase group delay
cs5378 ds639f1 49 filter type filter coefficients (normalized 24-bit) fir1 (coefficient set 0) low pass, sinc compensation linear phase decimate by 4 48 coefficients h 0 = 558 h 24 = 8388607 h 1 = 1905 h 25 = 7042723 h 2 = 3834 h 26 = 4768946 h 3 = 5118 h 27 = 2266428 h 4 = 365 h 28 = 189436 h 5 = -14518 h 29 = -1053303 h 6 = -39787 h 30 = -1392827 h 7 = -67365 h 31 = -1084130 h 8 = -69909 h 32 = -496361 h 9 = -19450 h 33 = 39864 h 10 = 97434 h 34 = 332367 h 11 = 258881 h 35 = 375562 h 12 = 375562 h 36 = 258881 h 13 = 332367 h 37 = 97434 h 14 = 39864 h 38 = -19450 h 15 = -496361 h 39 = -69909 h 16 = -1084130 h 40 = -67365 h 17 = -1392827 h 41 = -39787 h 18 = -1053303 h 42 = -14518 h 19 = 189436 h 43 = 365 h 20 = 2266428 h 44 = 5118 h 21 = 4768946 h 45 = 3834 h 22 = 7042723 h 46 = 1905 h 23 = 8388607 h 47 = 558 fir1 (coefficient set 1) low pass, sinc compensation minimum phase decimate by 4 48 coefficients h 0 = 3337 h 24 = 555919 h 1 = 22258 h 25 = -165441 h 2 = 88284 h 26 = -581479 h 3 = 266742 h 27 = -617500 h 4 = 655747 h 28 = -388985 h 5 = 1371455 h 29 = -99112 h 6 = 2502684 h 30 = 114761 h 7 = 4031988 h 31 = 186557 h 8 = 5783129 h 32 = 141374 h 9 = 7396359 h 33 = 58582 h 10 = 8388607 h 34 = -12664 h 11 = 8325707 h 35 = -42821 h 12 = 6988887 h 36 = -35055 h 13 = 4531706 h 37 = -16792 h 14 = 1507479 h 38 = 367 h 15 = -1319126 h 39 = 7929 h 16 = -3207750 h 40 = 5926 h 17 = -3736028 h 41 = 2892 h 18 = -2980701 h 42 = 23 h 19 = -1421498 h 43 = -1164 h 20 = 237307 h 44 = -538 h 21 = 1373654 h 45 = -238 h 22 = 1711919 h 46 = 18 h 23 = 1322371 h 47 = 113 figure 27. fi r1 coefficients
cs5378 ds639f1 50 filter type filter coefficients (normalized 24-bit) fir2 (coefficient set 0) low pass, passband to 40% f s linear phase decimate by 2 126 coefficients h 0 = -71 h 63 = 8388607 h 1 = -371 h 64 = 3875315 h 2 = -870 h 65 = -766230 h 3 = -986 h 66 = -1854336 h 4 = 34 h 67 = -137179 h 5 = 1786 h 68 = 1113788 h 6 = 2291 h 69 = 454990 h 7 = 291 h 70 = -642475 h 8 = -2036 h 71 = -553873 h 9 = -943 h 72 = 298975 h 10 = 2985 h 73 = 533334 h 11 = 3784 h 74 = -49958 h 12 = -1458 h 75 = -443272 h 13 = -5808 h 76 = -116005 h 14 = -1007 h 77 = 318763 h 15 = 7756 h 78 = 208018 h 16 = 5935 h 79 = -187141 h 17 = -7135 h 80 = -238025 h 18 = -11691 h 81 = 68863 h 19 = 3531 h 82 = 221211 h 20 = 17500 h 83 = 22850 h 21 = 4388 h 84 = -174452 h 22 = -20661 h 85 = -81993 h 23 = -15960 h 86 = 114154 h 24 = 18930 h 87 = 109009 h 25 = 29808 h 88 = -54172 h 26 = -9795 h 89 = -109189 h 27 = -42573 h 90 = 4436 h 28 = -7745 h 91 = 90744 h 29 = 49994 h 92 = 29702 h 30 = 33021 h 93 = -62651 h 31 = -47092 h 94 = -47092 h 32 = -62651 h 95 = 33021 h 33 = 29702 h 96 = 49994 h 34 = 90744 h 97 = -7745 h 35 = 4436 h 98 = -42573 h 36 = -109189 h 99 = -9795 h 37 = -54172 h 100 = 29808 h 38 = 109009 h 101 = 18930 h 39 = 114154 h 102 = -15960 h 40 = -81993 h 103 = -20661 h 41 = -174452 h 104 = 4388 h 42 = 22850 h 105 = 17500 h 43 = 221211 h 106 = 3531 h 44 = 68863 h 107 = -11691 h 45 = -238025 h 108 = -7135 h 46 = -187141 h 109 = 5935 h 47 = 208018 h 110 = 7756 h 48 = 318763 h 111 = -1007 h 49 = -116005 h 112 = -5808 h 50 = -443272 h 113 = -1458 h 51 = -49958 h 114 = 3784 h 52 = 533334 h 115 = 2985 h 53 = 298975 h 116 = -943 h 54 = -553873 h 117 = -2036 h 55 = -642475 h 118 = 291 h 56 = 454990 h 119 = 2291 h 57 = 1113788 h 120 = 1786 h 58 = -137179 h 121 = 34 h 59 = -1854336 h 122 = -986 h 60 = -766230 h 123 = -870 h 61 = 3875315 h 124 = -371 h 62 = 8388607 h 125 = -71 figure 28. fir2 linear phase coefficients
cs5378 ds639f1 51 filter type filter coefficients (normalized 24-bit) fir2 (coefficient set 1) low pass, passband to 40% f s minimum phase decimate by 2 126 coefficients h 0 = 4019 h 63 = 67863 h 1 = 43275 h 64 = -190800 h 2 = 235427 h 65 = -128546 h 3 = 848528 h 66 = 114197 h 4 = 2240207 h 67 = 147750 h 5 = 4525758 h 68 = -46352 h 6 = 7077833 h 69 = -143269 h 7 = 8388607 h 70 = -13290 h 8 = 6885673 h 71 = 114721 h 9 = 2483461 h 72 = 51933 h 10 = -2538963 h 73 = -75952 h 11 = -4800543 h 74 = -68746 h 12 = -2761696 h 75 = 38171 h 13 = 1426109 h 76 = 68492 h 14 = 3624338 h 77 = -7856 h 15 = 1820814 h 78 = -57526 h 16 = -1695825 h 79 = -12540 h 17 = -2885148 h 80 = 41717 h 18 = -605252 h 81 = 23334 h 19 = 2135021 h 82 = -25516 h 20 = 1974197 h 83 = -26409 h 21 = -630111 h 84 = 11717 h 22 = -2168177 h 85 = 24246 h 23 = -750147 h 86 = -1620 h 24 = 1516192 h 87 = -19248 h 25 = 1550127 h 88 = -4610 h 26 = -508445 h 89 = 13356 h 27 = -1686937 h 90 = 7526 h 28 = -437822 h 91 = -7887 h 29 = 1308705 h 92 = -8016 h 30 = 1069556 h 93 = 3559 h 31 = -657282 h 94 = 7023 h 32 = -1301014 h 95 = -598 h 33 = -30654 h 96 = -5350 h 34 = 1173754 h 97 = -1097 h 35 = 579643 h 98 = 3579 h 36 = -803111 h 99 = 1806 h 37 = -895851 h 100 = -2058 h 38 = 328399 h 101 = -1859 h 39 = 962522 h 102 = 936 h 40 = 124678 h 103 = 1558 h 41 = -820948 h 104 = -224 h 42 = -466657 h 105 = -1129 h 43 = 545674 h 106 = -152 h 44 = 652827 h 107 = 718 h 45 = -220448 h 108 = 290 h 46 = -680495 h 109 = -395 h 47 = -80886 h 110 = -290 h 48 = 578844 h 111 = 178 h 49 = 306445 h 112 = 227 h 50 = -395302 h 113 = -53 h 51 = -431004 h 114 = -151 h 52 = 181900 h 115 = -5 h 53 = 454403 h 116 = 86 h 54 = 15856 h 117 = 23 h 55 = -395525 h 118 = -42 h 56 = -166123 h 119 = -22 h 57 = 284099 h 120 = 17 h 58 = 253485 h 121 = 14 h 59 = -152407 h 122 = -5 h 60 = -277888 h 123 = -7 h 61 = 28526 h 124 = 1 h 62 = 250843 h 125 = 3 figure 29. fir2 mini mum phase coefficients
cs5378 ds639f1 52 14. iir filter the infinite impulse res ponse (iir) filter block consists of two cascaded stages, iir1 and iir2. it creates a high-pass corner to block very low-fre- quency and dc components of the input signal. on-chip iir1 and iir2 coe fficients can be selected using a configuration comm and, or the coefficients can be programmed for a custom filter response. 14.1 iir architecture the architecture of the ii r filter is automatically determined when the output filter stage is selected in the filtcfg register. selecting the 1st order iir1 filter bypasses the 2nd order stage, while se- lecting the 2nd order iir2 filter bypasses the 1st or- der stage. selection of the 3rd order iir3 filter enables both the 1st and 2nd order stages. 14.2 iir1 filter the 1st order iir filter stag e is a direct form filter with three coefficients : a11, b10, and b11. coeffi- cients of a 1st order ii r are inherently normalized to one, and should be scal ed to 24-bit two?s com- plement full scale, 0x7fffff. the characteristic equations for the 1st order iir include an input value, x, an output value, y, and two intermediate values, w1 and w2, separated by a delay element (z -1 ). w2 = w1 w1 = x + (-a11 * w2) y = (w1 * b10) + (w2 * b11) 14.3 iir2 filter the 2nd order iir filter stage is a direct form filter with five coefficients: a21, a22, b20, b21, and b22. coefficients of a 2nd orde r iir are inherently nor- malized to two, and shoul d be scaled to 24-bit two?s complement full s cale, 0x7fffff. normal- ization effectively divi des the 2nd order coeffi- cients in half relative to the input, and requires modification of the ch aracteristic equations. the characteristic equations for the 2nd order iir include an input value, x, an output value, y, and three intermediate valu es, w3, w4, and w5, each separated by a delay element (z -1 ). the following z -1 z -1 z -1 -a 11 b 11 b 10 -a 21 -a 22 b 21 b 22 b 20 figure 30. iir fi lter block diagram 1st order iir1 2nd order iir2 3rd order iir3 implemented by running both iir1 and iir2 stages
cs5378 ds639f1 53 characteristic equations model the operation of the 2nd order iir filter with unnormalized coefficients. w5 = w4 w4 = w3 w3 = x + (-a21 * w4) + (-a22 * w5) y = (w3 * b20) + (w4 * b21) + (w5 * b22) internally, the cs5378 uses normalized coeffi- cients to perform the 2nd order iir filter calcula- tion, which changes the al gorithm slightly. the following characteristic equations model the oper- ation of the 2nd order iir filter when using normal- ized coefficients. w5 = w4 w4 = w3 w3 = 2 * [(x / 2) + (-a21 * w4) + (-a22 * w5)] y = 2 * [(w3 * b20) + (w4 * b21) + (w5 * b22)] 14.4 iir3 filter the 3rd order iir filter is implemented by running both the 1st order and 2nd orde r iir filter stages. it can be modeled by cascad ing the characteristic equations of the 1st orde r and 2nd order iir stages. 14.5 on-chip iir coefficients five sets of on-chip coef ficients are available for iir1 and iir2, each pr oviding a 3 hz high-pass butterworth response at different output word rates. characteristics of the on-chip coefficient sets are described in figure 31 and table 16. which on-chip coefficient se t to use is selected by a data word following the ?write rom coeffi- cients? configuration comm and. see ?filter coef- ficient selection? on pa ge 38 for information about selecting on-chip coefficient sets. 14.6 programmable iir coefficients a maximum of 3 + 5 coefficients can be pro- grammed into iir1 and iir2 to create a custom fil- ter response. custom fi lter sets should normalize the coefficients to 24-bi t two?s complement full scale, 0x7fffff. to ma intain maximum internal dynamic range, the cs5378 iir filter performs double precision calculati ons with an automatic gain correction to scale the final output. custom iir coefficients are uploaded using the ?write iir coefficients ? configuration command. see ?eeprom configuration commands? on page 27 or ?microcontroll er configuration com- mands? on page 33 for information about writing custom iir coefficients. 14.7 iir filter synchronization the iir filter is not sync hronized to the external system directly, only i ndirectly through the syn- chronization of the sinc and fir filters. because iir filters have ?infinite ? memory, a discontinuity in the input data stream from a synchronization event can require significant time to settle out. the exact settling time depends on the size of the dis- continuity and the filter coefficient characteristics.
cs5378 ds639f1 54 iir1 ? single stage, no decimation 1 st order no decimation, 3 coefficients coefficient set 0: high-pass, corner 0.15% f s (3 hz at 2000 sps) coefficient set 1: high-pass, corner 0.30% f s (3 hz at 1000 sps) coefficient set 2: high-pass, corner 0.60% f s (3 hz at 500 sps) coefficient set 3: high-pass, corner 0.90% f s (3 hz at 333 sps) coefficient set 4: high-pass, corner 1.20% f s (3 hz at 250 sps) iir2 ? single stage, no decimation 2 nd order no decimation, 5 coefficients coefficient set 0: high-pass, corner 0.15% f s (3 hz at 2000 sps) coefficient set 1: high-pass, corner 0.30% f s (3 hz at 1000 sps) coefficient set 2: high-pass, corner 0.60% f s (3 hz at 500 sps) coefficient set 3: high-pass, corner 0.90% f s (3 hz at 333 sps) coefficient set 4: high-pass, corner 1.20% f s (3 hz at 250 sps) iir3 ? two stage, no decimation 3 rd order no decimation, 8 coefficients (combined iir1 and iir2 filter responses) coefficient set 0,0: high-pass, corner 0.20% f s (4 hz at 2000 sps) coefficient set 1,1: high-pass, corner 0.41% f s (4 hz at 1000 sps) coefficient set 2,2: high-pass, corner 0.82% f s (4 hz at 500 sps) coefficient set 3,3: high-pass, corner 1.22% f s (4 hz at 333 sps) coefficient set 4,4: high-pass, corner 1.63% f s (4 hz at 250 sps) figure 31. iir filter stages iir filters iir1 coeff selection iir1 corner frequency iir2 coeff selection iir2 corner frequency iir3 coeff selection iir3 corner frequency 0 0.15% f s 0 0.15% f s 0,0 0.2041% f s 1 0.30% f s 1 0.30% f s 1,1 0.4074% f s 2 0.60% f s 2 0.60% f s 2,2 0.8152% f s 3 0.90% f s 3 0.90% f s 3,3 1.2222% f s 4 1.20% f s 4 1.20% f s 4,4 1.6293% f s table 16. iir filter characteristics
cs5378 ds639f1 55 filter type system function filter coefficients (normalized 24-bit) iir1 (coefficient set 0) 1 st order, high pass corner at 0.15% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8309916 b 10 = 8349262 b 11 = -8349262 iir1 (coefficient set 1) 1 st order, high pass corner at 0.30% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8231957 b 10 = 8310282 b 11 = -8310282 iir1 (coefficient set 2) 1 st order, high pass corner at 0.60% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -8078179 b 10 = 8233393 b 11 = -8233393 iir1 (coefficient set 3) 1 st order, high pass corner at 0.90% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -7927166 b 10 = 8157887 b 11 = -8157887 iir1 (coefficient set 4) 1 st order, high pass corner at 1.20% f s 3 coefficients ? ? ? ? ? ? ? ? + + = ? ? 1 11 1 11 10 1 ) ( z a z b b z h a 11 = -7778820 b 10 = 8083714 b 11 = -8083714 filter type system function filter coefficients (normalized 24-bit) iir2 (coefficient set 0) 2 nd order, high pass corner at 0.15% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8332704 a 22 = 4138771 b 20 = 4166445 b 21 = -8332890 b 22 = 4166445 iir2 (coefficient set 1) 2 nd order, high pass corner at 0.30% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8276806 a 22 = 4083972 b 20 = 4138770 b 21 = -8277540 b 22 = 4138770 iir2 (coefficient set 2) 2 nd order, high pass corner at 0.60% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8165041 a 22 = 3976543 b 20 = 4083972 b 21 = -8167944 b 22 = 4083972 iir2 (coefficient set 3) 2 nd order, high pass corner at 0.90% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -8053350 a 22 = 3871939 b 20 = 4029898 b 21 = -8059796 b 22 = 4029898 iir2 (coefficient set 4) 2 nd order, high pass corner at 1.20% f s 5 coefficients ? ? ? ? ? ? ? ? + + + + = ? ? ? ? 1 22 1 21 1 22 1 21 20 1 ) ( z a z a z b z b b z h a 21 = -7941764 a 22 = 3770088 b 20 = 3976539 b 21 = -7953078 b 22 = 3976539 table 17. iir filter coefficients
cs5378 ds639f1 56 15. gain and offs et correction the cs5378 digital filter can apply gain and offset corrections to the measurem ent data. also, an off- set calibration al gorithm can automatically calcu- late the offset correction value. a gain correction value is written to the gain reg- isters (0x21), while an offset correction value is written to the offset re gister (0x25). gain and offset corrections are enabled by the usegr and useor bits in the fi ltcfg register (0x20). when enabled, the offset calibration algorithm will automatically calculate an offset correction value and write it into the offse t register. offset cali- bration is enabled by wr iting the exp and orcal bits in filtcfg. 15.1 gain correction gain correction in the cs5378 normalizes sensor gain in multi-sensor netw orks. it requires an exter- nally calculated correction value to be written into the gain register (0x21). a gain correction value is 24-bit two?s complement with unity gain defined as full scale, 0x7fffff. gain correction always scal es to a fractional value, and can never gain the digi tal filter data greater than one. output value = data * (gain / 0x7fffff) unity gain: gain = 0x7fffff 50% gain: gain = 0x3fffff zero gain: gain = 0x000000 once the gain register is written, the usegr bit in the filtcfg register enables gain correction. 15.2 offset correction offset correction in the cs5378 cancels the dc bias of a measurement ch annel by subtracting the value in the offset register (0x25) from the dig- ital filter output data word. an offset correction valu e is 24-bit two?s comple- ment with a maximum pos itive value of 0x7fffff, figure 32. gain and offset correction fir iir filters filter output to high speed seri al data port (sd port) offset correction output rate 4000 sps ~ 1 sps sinc filter mdi input 512 khz correction gain offset calibration
cs5378 ds639f1 57 and a maximum negative value of 0x800000. if ap- plying an offset correcti on causes the final result to exceed a 24-bit two?s complement maximum, the output data will saturate to that maximum value. output data = input data - offset correction max positive output value = 0x7fffff max negative output value = 0x800000 once the offset register is written, the useor bit in the filtcfg register enables offset correc- tion. 15.3 offset calibration an offset calibration al gorithm in the cs5378 can automatically calculate an offset correction value. when using the offset cal ibration algorithm, back- ground noise data should be used as the input signal for calculating the offset of the measurement chan- nel. the offset calibration algo rithm is an exponential averaging function that pl aces increased weight on more recent digital filter data. the exponential weighting factor is set by the exp bits in the filtcfg register, with larger exponent values producing a smoother averaging function that re- quires a longer settling ti me, and smaller values producing a noisier averaging function that re- quires a shorter settling time. typical exponential values range from 0x05 to 0x0f, depending on the available settling time. the characteristic equations of the offset calibra- tion algorithm include an input value, x, an output value, y, a summation value, ysum, a sample in- dex, n, and an exponential value, exp. y(n) = x(n) - [ysum(n-1) >> exp] ysum(n) = y(n) + ysum(n-1) offset correction = ysum >> exp once the exp bits are written, the orcal bit in the filtcfg register is set to enable offset calibra- tion. when enabled, an updated offset correction value is automatically written to the offset reg- ister. when the offset cal ibration algorithm is fully settled, the orcal bit shoul d be cleared to main- tain the final value in the offset register.
cs5378 ds639f1 58 16. serial data interface once digital filtering is co mplete, each 24-bit out- put sample is combined with an 8-bit status byte. these data words are writt en to an 8-deep fifo buffer and then transmit ted to the communications channel through a high speed serial data interface. 16.1 pin descriptions drdy - pin 23 data ready output signal, ac tive low. open drain output requiring an external pull-up resistor. sck - pin 24 serial clock input. miso - pin 25 serial data output. 16.2 serial data format serial data transactions transfer either 24-bit data words or 32-bit status+data words, depending on the stat bit in the config register. when trans- mitting status information, each 8-bit status byte has an mflag bit, a time break bit, and a fifo overflow bit encoded as shown in figure 34. mflag bit - mflag the mflag bit is set in the status byte when an signal is received on the mflag pin. when re- cs5378 figure 33. serial data interface block diagram system telemetry miso drdy sck data ready data in clock out data status 0 23 31 -- mflag -- -- w 31 29 30 28 27 26 25 24 figure 34. 32-bit serial data format tb -- -- 0 - modulator ok 1 - modulator error 0 - no time break 1 - time break 0 - fifo ok 1 - fifo overflow
cs5378 ds639f1 59 ceived, the mflag bit is set in the next output word. see ?modulator interface? on page 36 for more information about mflag. time break bit - tb the time break bit marks a timing reference based on a rising edge into the timeb pin. after a pro- grammed delay, the tb bit in the status byte is set for one output sample. the timebrk digital fil- ter register (0x29) program s the sample delay for the tb bit output. see ?t ime break controller? on page 63 for more information about time break. fifo overflow bit - w the fifo overflow bit indicates an error condition in the serial data fifo, a nd is set if new digital fil- ter data overwrites a fifo location containing data which has not yet been sent. the w bit is sticky, meani ng it persists indefinitely once set. clearing the w bit requires sending the ?filter stop? and ?filter start? configuration com- mands to reinitialize the data fifo. conversion data word the lower 24-bits of the seri al data word is the con- version sample for the specified channel. conver- sion data is 24-bit two? s complement format. 16.3 serial data transactions the cs5378 automatically initiates serial data transactions whenever da ta becomes available in the output fifo by driving the drdy pin low. once a serial data transaction is initiated, serial clocks received into sck ca use data to be output to miso, as shown in figure 35. when all available data is read from the serial data fifo, drdy is re- leased. drdy sck miso figure 35. sd po rt transaction msb lsb
cs5378 ds639f1 60 17. test bit stream generator the cs5378 test bit stream (tbs) generator creates sine wave or impulse ? bit stream data to drive an external test dac. the tbs digital output can also be internally connected to the mdata inputs for loopback testing of the digital filter. 17.1 pin descriptions tbsdata - pin 8 test bit stream 1-bit ? data output. mclk - pin 11 test bit stream clock output. 17.2 tbs architecture the test bit stream generato r consists of a data in- terpolator and a digital ? modulator. it receives periodic 24-bit data from th e digital filter to create a 1-bit ? data output on the tbsdata pin. the tbs input data from th e digital filter is scaled by the tbsgain register (0x2b). maximum sta- ble amplitude is 0x04ff ff, with 0x04b000 ap- proximately full scale for the cs4373 test dac. the full scale 1-bit ? output from the tbs gener- ator is defined as 25% minimum and 75% maxi- mum one?s density. 17.3 tbs configuration configuration options for the tbs generator are set through the tbscfg register (0x2a). gain scal- ing of the tbs generator output is set by the tb- sgain register (0x2b). interpolation factor - intp[7:0] selects how many times the interpolator uses a data point when generating the ou tput bit stream. inter- polation is zero based a nd represents one greater than the programmed register value. operational mode - tmode selects between sine wave or impulse output mode. output rate - rate[2:0] selects the tbsdata output rate. synchronization - tsync enables synchronization of the tbs output phase to the msync signal. loopback - loop enables digital loopback from the tbs output to the mdata inputs. digital ? modulator 24-bit 1-bit tbsdata digital filter tbsgain register 24-bit figure 36. test bit stream generator block diagram data bus
cs5378 ds639f1 61 run - run enables the test bit stream generator. data delay - ddly[5:0] programs full period delays for tbsdata, up to a maximum of 63 bits. gain - tbsgain[23:0] scales the amplitude of the sine wave output and generated impulse. maximum 0x04ffff, nominal 0x04b000. 17.4 tbs data source an on-chip 24-bit 1024 point digital sine wave is stored on the cs5378 wh ich will produce the test signal frequencies listed in table 18. additional discrete test frequencie s and output rates can be programmed by varying th e interpolation factor and output rate. 17.5 tbs sine wave output when the tmode bit in the tbscfg register is low, the tbs generator operates in sine wave mode. in this mode, sine wave data from digital fil- ter memory is used to creat e a sine wave test signal that can drive a test dac. sine wave frequency and output data rate are ca lculated as shown by the characteristic equation of table 18. the sine wave maximum ? one?s density output from the tbs generator is set by the tbsgain register. tbsgain can be programmed up to a maximum of 0x04ffff, with the tbs generator unstable for higher amplitudes. for the cs4373 test dac, a gain value of 0x04b000 produces an approximately full scal e sine wave output (5 v pp differential). test bit stream charac teristic equation: (signal freq) * (# tbs data) * (interpolation + 1) = output rate example: (31.25 hz) * (1024) * (0x07 + 1) = 256 khz signal frequency (tbsdata) output rate (tbsclk) output rate selection (rate) interpolation selection (intp) 10.00 hz 256 khz 0x4 0x18 10.00 hz 512 khz 0x5 0x31 25.00 hz 256 khz 0x4 0x09 25.00 hz 512 khz 0x5 0x13 31.25 hz 256 khz 0x4 0x07 31.25 hz 512 khz 0x5 0x0f 50.00 hz 256 khz 0x4 0x04 50.00 hz 512 khz 0x5 0x09 125.00 hz 256 khz 0x4 0x01 125.00 hz 512 khz 0x5 0x03 table 18. tbs configurations using on-chip data
cs5378 ds639f1 62 17.6 tbs impulse output if the tmode bit in tbsc fg is set high, the tbs generator operates in impulse mode. in this mode, the value in tbsgain sets the amplitude of the generated impulse. impul se amplitude and period are shown in table 19. to create a maximum im pulse from the tbs gen- erator, the tbsgain register should be set to 0x04ffff, and the intp bits in tbscfg should also be set to 0xff. the rate bits should always be set to produce data at th e correct rate for the in- tended test dac. a rising edge on the time b pin triggers the im- pulse output. when impulse mode is enabled but no timeb input is receiv ed, the tbs generator uses a negated tbsgain regi ster as a repetitive in- put value. when a rising edge is recognized on the timeb pin, a single pos itive tbsgain value is written to the tbs generator to create the impulse. 17.7 tbs loopback testing included as part of the cs5378 test bit stream gen- erator is a feedback path to the digital filter mda- ta input. this loopback mode provides a fully digital signal path to test the tbs generator, digital filter, and data collecti on interface. digital loop- back testing expects 512 khz ? data into the mdata input. a mismatch of the tbs ge nerator full scale output and the mdata full scale input results in an am- plitude mismatch when te sting in loopback mode. the tbs generator outputs a 75% maximum one?s density, while the mdat a inputs expect an 86% maximum one?s density from a ? modulator, re- sulting in a measured full scale error of approxi- mately -3.6 db. 17.8 tbs synchronization when the tsync bit is se t in the tbscfg regis- ter, the msync signal rese ts the sine wave data pointer and phase aligns the tbs signal output. once the digital filter is settled, all cs5378 devices receiving the sync signal w ill have identical tbs signal phase. see ?sync hronization? on page 24 for more information about the sync and msync signals. if tsync is clear, msync has no effect on the tbs data pointer and no change in the tbs output phase will occur during synchronization. test bit stream impulse characteristics: interpolation selection (intp) output rate selection (rate) pulse width from cs4373 gain scale factor (tbsgain) pulse height from cs4373 0xff 0x5 500 s 0x04b000 ~ 860 mv 0xff 0x4 1 ms 0x04b000 ~ 820 mv 0xff 0x3 2 ms 0x04b000 ~ 820 mv 0x7f 0x5 250 s 0x04b000 ~ 820 mv 0x7f 0x4 500 s 0x04b000 ~ 820 mv 0x7f 0x3 1 ms 0x04b000 ~ 820 mv table 19. tbs impulse characteristics
cs5378 ds639f1 63 18. time break controller a time break signal is us ed to mark timing events that occur during measurem ent. an external signal sets a flag in the status byte of an output sample to mark when the external event occurred. a rising edge input to th e timeb pin causes the tb timing reference flag to be set in the serial data status byte. when set, th e tb flag appears for only one output sample in the st atus byte. the tb flag output can be delayed by programming a sample delay value into the time brk digital filter regis- ter. 18.1 pin description timeb - pin 20 time break input pin, rising edge triggered. 18.2 time break operation an externally generated timing reference signal ap- plied to the timeb pin init iates an internal sample counter. after a number of output samples have passed, programmed in th e timebrk digital filter register (0x29), the tb flag is set in the status byte of the serial data output wo rd. the tb flag is auto- matically cleared for subs equent data words, and appears for only one output sample. 18.3 time break delay the timebrk register (0x29) sets a sample delay between a received rising edge on the timeb pin and writing the tb flag into the serial data status byte. the programmable sample counter can compensate for group delay through the di gital filters. when the proper group delay value is programmed into the timebrk register, the tb fl ag will be set in the status byte of the measurement sample taken when the timing reference signal was received. 18.3.1 step input and group delay a simple method to empirically measure the step response and group dela y of a cs5378 measure- ment channel is to use th e time break signal as both a timing reference input and an analog step input. when a rising edge is received on the timeb pin with no delay programmed into the timebrk reg- ister, the tb flag is set in the next serial data status byte. the same rising edge can act as a step input to the analog channel, propagating through the dig- ital filter to appear as a rising edge in the measure- ment data. by compar ing the timing of the tb status flag output and th e rising edge in the mea- surement data, the meas urement channel group de- lay can be determined. timeb in serial data status byte delay counter timebrk tb flag figure 37. time break block diagram
cs5378 ds639f1 64 19. general purpose i/o the general purpose i/o (gpio) block provides 8 general purpose pins to interface with external hardware. 19.1 pin descriptions gpio[3:0] - pins 4 - 1 standard gpio pins. gpio[6:4]:pll[2:0] - pins 7 - 5 standard gpio pins also used to select the pll mode after reset. inte rnal pull-ups default high, 10 k ? external pull-downs required to set low. gpio7:boot - pin 28 standard gpio pin also used to select boot mode after reset. internal pul l-up defaults high, 10 k ? ex- ternal pull-down required to set low. 19.2 gpio architecture each gpio pin can be conf igured as input or out- put, high or low, with a weak (~100 k ? ) internal pull-up resistor enabled or disabled. figure 38 shows the structure of a bi-directional gpio pin. 19.3 gpio registers gpio pin settings are programmed in the gpcfg register. gp_dir bits se t the input/output mode, gp_pull bits enable/disable the internal pull-up resistor, and gp_data bits set the output data val- ue. after reset, gpio pi ns default as inputs with pull-up resistors enabled. 19.4 gpio input mode when reading a value from the gp_data bits, the returned data reports the cu rrent state of the pins. if a pin is externally driven high it reads a logical 1, if externally driven low it reads a logical 0. when a gpio pin is used as an input, the pull-up resistor should be disabled to save power if it isn?t required. 19.5 gpio output mode when a gpio pin is progr ammed as an output with a data value of 0, the pin is driven low and the in- ternal pull-up resi stor is automatically disabled. when programmed as an ou tput with a data value of 1, the pin is driven high and the pull-up resistor is inconsequential. any gpio pin can be used as an open-drain output by setting the data value to 0, enabling the pull-up, and using the gp_dir direction bits to control the pin value. this open-dr ain output configuration uses the internal pull-up resistor to hold the pin high when gp_dir is set as an input, and drives the pin low when gp_dir is set as an output. figure 38. gpio block diagram gpio gp_dir gp_data gp_pull pull up logic r
cs5378 ds639f1 65 19.5.1 gpio reads in output mode when reading gpio pins the gp_data register value always reports the cu rrent state of the pins, so a value written in output mode does not necessarily read back the same value. if a pin in output mode is written as a logical 1, th e cs5378 attempts to drive the pin high. if an external device forces the pin low, the read value reflects the pin state and returns a logical 0. similarly, if an output pin is written as a logical 0 but forced high externally, the read val- ue reflects the pin state and returns a logical 1. in both cases the cs5378 is in contention with the ex- ternal device resulting in increased power con- sumption.
cs5378 ds639f1 66 20. register summary 20.1 spi registers the cs5378 spi registers interface the serial port to the digital filter. name addr. type # bits description spictrlh 00 r/w 8 spi control register, high byte spictrlm 01 r/w 8 spi control register, middle byte spictrll 02 r/w 8 spi control register, low byte spicmdh 03 r/w 8 spi command, high byte spicmdm 04 r/w 8 spi command, middle byte spicmdl 05 r/w 8 spi command, low byte spidat1h 06 r/w 8 spi data 1, high byte spidat1m 07 r/w 8 spi data 1, middle byte spidat1l 08 r/w 8 spi data 1, low byte spidat2h 09 r/w 8 spi data 2, high byte spidat2m 0a r/w 8 spi data 2, middle byte spidat2l 0b r/w 8 spi data 2, low byte
cs5378 ds639f1 67 20.1.1 spictrl : 0x00, 0x01, 0x02 (msb) 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- r/w r/w1 r/w r/w r/w r/w r/w r/w 00001011 15 14 13 12 11 10 9 8 smodf----emopswef----e2dreq r r/w r r r r/w r/w r/w 00000010 7654321(lsb) 0 -- -- -- -- -- -- -- -- r/wr/wr/wr/wr/wr/wr/wr/w 00100000 spi address: 0x00 0x01 0x02 -- not defined; read as 0 rreadable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: 23:16 -- reserved 15 smodf spi mode fault flag 7:0 -- reserved 14:13 -- reserved 12 emop external master to spi operation in progress flag 11 swef spi write collision error flag 10:9 -- reserved 8 e2dreq external master to digital filter request flag figure 39. spi control register spictrl
cs5378 ds639f1 68 20.1.2 spicmd : 0x03, 0x04, 0x05 (msb) 23 22 21 20 19 18 17 16 scmd23 scmd22 scmd21 scmd20 scmd19 scmd18 scmd17 scmd16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 scmd15 scmd14 scmd13 scmd12 scmd11 scmd10 scmd9 scmd8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 scmd7 scmd6 scmd5 scmd4 scmd3 scmd2 scmd1 scmd0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 spi address: 0x03 0x04 0x05 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 40. spi command register spicmd bit definitions: 23:16 scmd[23:16] spi command high byte 15:8 scmd[15:8] spi command mid- dle byte 15:8 scmd[7:0] spi command low byte
cs5378 ds639f1 69 20.1.3 spidat1 : 0x06, 0x07, 0x08 (msb) 23 22 21 20 19 18 17 16 sdat23 sdat22 sdat21 sdat20 sdat19 sdat18 sdat17 sdat16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 sdat15 sdat14 sdat13 sdat12 sdat11 sdat10 sdat9 sdat8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 sdat7 sdat6 sdat5 sdat4 sdat3 sdat2 sdat1 sdat0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 spi address: 0x06 0x07 0x08 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 41. spi data register spidat1 bit definitions: 23:16 sdat[23:16] spi data high byte 15:8 sdat[15:8] spi data middle byte 15:8 sdat[7:0] spi data low byte
cs5378 ds639f1 70 20.1.4 spidat2 : 0x09, 0x0a, 0x0b (msb) 23 22 21 20 19 18 17 16 sdat23 sdat22 sdat21 sdat20 sdat19 sdat18 sdat17 sdat16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 sdat15 sdat14 sdat13 sdat12 sdat11 sdat10 sdat9 sdat8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 sdat7 sdat6 sdat5 sdat4 sdat3 sdat2 sdat1 sdat0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 spi address: 0x09 0x0a 0x0b -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 42. spi data register spidat2 bit definitions: 23:16 sdat[23:16] spi data high byte 15:8 sdat[15:8] spi data middle byte 15:8 sdat[7:0] spi data low byte
cs5378 ds639f1 71 20.2 digital filter registers the cs5378 digital filter registers control ha rdware peripherals a nd filtering functions. name addr. type # bits description config 00 r/w 24 hardware configuration reserved 01-0d r/w 24 reserved gpcfg 0e r/w 24 gpio[7:0] directi on, pull-up enable, and data reserved 0f-1f r/w 24 reserved filtcfg 20 r/w 24 digital filter configuration gain 21 r/w 24 gain correction reserved 22-24 r/w 24 reserved offset 25 r/w 24 offset correction reserved 26-28 r/w 24 reserved timebrk 29 r/w 24 time break delay tbscfg 2a r/w 24 test bit stream configuration tbsgain 2b r/w 24 test bit stream gain system1 2c r/w 24 user defined system register 1 system2 2d r/w 24 user defined system register 2 version 2e r/w 24 hardware version id selftest 2f r/w 24 self-test result code
cs5378 ds639f1 72 20.2.1 config : 0x00 (msb)2322212019181716 -- -- -- -- -- dfs2 dfs1 dfs0 r/w r/w r/w r/w r/w r/w r/w r/w 00000101 15 14 13 12 11 10 9 8 -- -- -- -- -- mckfs2 mckfs1 mckfs0 r/w r/w r/w r/w r/w r/w r/w r/w 00000100 7654321(lsb)0 stat -- mcken2 mcken mdifs -- boot msen r/w r/w r/w r/w r/w r/w r r/w 00000001 figure 43. hardware configuration register config bit definitions: 23:19 -- reserved 15:11 -- reserved 7:6 stat serial data status byte 1: disabled (24-bit output) 0: enabled (32-bit output) 18:16 dfs [2:0] digital filter frequency select 111: reserved 110: 8.192 mhz 101: 4.096 mhz 100: 2.048 mhz 011: 1.024 mhz 010: 512 khz 001: 256 khz 000: 32 khz 10:8 mckfs [2:0] mclk frequency select 111: reserved 110: reserved 101: 4.096 mhz 100: 2.048 mhz 011: 1.024 mhz 010: 512 khz 001: reserved 000: reserved 5 mcken2 mclk/2 output enable 1: enabled 0: disabled 4 mcken mclk output enable 1: enabled 0: disabled 3 mdifs mdata input frequency select 1: 256 khz 0: 512 khz 2 -- reserved 1 boot boot source indicator 1: booted from eeprom 0: booted from micro 0 msen msync enable 1: msync generated 0: msync remains low df address: 0x00 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition
cs5378 ds639f1 73 20.2.2 gpcfg : 0x0e (msb) 23 22 21 20 19 18 17 16 gp_dir7 gp_dir6 gp_dir5 gp_dir4 gp_dir3 gp_dir2 gp_dir1 gp_dir0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 gp_pull7 gp_pull6 gp_pull5 gp_pull4 gp_pull3 gp_pull2 gp_pull1 gp_pull0 r/wr/wr/wr/wr/wr/wr/wr/w 11111111 7654321(lsb) 0 gp_data7 gp_data6 gp_data5 gp_data4 gp_data3 gp_data2 gp_data1 gp_data0 r/wr/wr/wr/wr/wr/wr/wr/w 11111111 df address: 0x0e -- not defined; read as 0 rreadable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: notes: gpio[7] also used as boot mode select after reset gpio[6:4] also used as pll mode select after reset. 23:16 gp_dir [7:0] gpio pin direction 1: output 0: input 15:8 gp_pull [7:0] gpio pullup resistor 1: enabled 0: disabled 7:0 gp_data [7:0] gpio data value 1: vdd 0: gnd figure 44. gpio configuration register gpcfg
cs5378 ds639f1 74 20.2.3 filtcfg : 0x20 (msb) 23 22 21 20 19 18 17 16 -- -- -- exp4 exp3 exp2 exp1 exp0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 -- orcal useor usegr -- fsel2 fsel1 fsel0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 dec3 dec2 dec1 dec0 -- -- -- -- r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x20 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition bit definitions: 23:21 -- reserved 15 -- reserved 7:4 dec[3:0] decimation selection (output word rate) 20:16 exp[4:0] offset calibration exponent 14 orcal run offset calibration 1: enable 0: disable 0111: 4000 sps 0110: 2000 sps 0101: 1000 sps 0100: 500 sps 0011: 333 sps 13 useor use offset correction 1: enable 0: disable 0010: 250 sps 0001: 200 sps 0000: 125 sps 1111: 100 sps 1110: 50 sps 12 usegr use gain correction 1: enable 0: disable 1101: 40 sps 1100: 25 sps 1011: 20 sps 1010: 10 sps 1001: 5 sps 1000: 1 sps 11 -- reserved 3:0 -- reserved 10:8 fsel[2:0] output filter stage select 111: reserved 110: reserved 101: iir 3rd order 100: iir 2nd order 011: iir 1st order 010: fir2 output 001: fir1 output 000: sinc output figure 45. filter configuration register filtcfg
cs5378 ds639f1 75 20.2.4 gain : 0x21 (msb) 23 22 21 20 19 18 17 16 gain23 gain22 gain21 gain20 gain19 gain18 gain17 gain16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 gain15 gain14 gain13 gain12 gain11 gain10 gain9 gain8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 gain7 gain6 gain5 gain4 gain3 gain2 gain1 gain0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x21 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 46. gain correction register gain bit definitions: 23:16 gain[23:16] gain correction upper byte 15:8 gain[15:8] gain correction middle byte 15:8 gain[7:0] gain correction lower byte
cs5378 ds639f1 76 20.2.5 offset : 0x25 (msb) 23 22 21 20 19 18 17 16 ofst23 ofst22 ofst21 ofst20 ofst19 ofst18 ofst17 ofst16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 ofst15 ofst14 ofst13 ofst12 ofst11 ofst10 ofst9 ofst8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 ofst7 ofst6 ofst5 ofst4 ofst3 ofst2 ofst1 ofst0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x25 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 47. offset correction register offset bit definitions: 23:16 ofst[23:16] offset correction upper byte 15:8 ofst[15:8] offset correction middle byte 15:8 ofst[7:0] offset correction lower byte
cs5378 ds639f1 77 20.2.6 timebrk : 0x29 (msb) 23 22 21 20 19 18 17 16 tbrk23 tbrk22 tbrk21 tbrk20 tbrk19 tbrk18 tbrk17 tbrk16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 tbrk15 tbrk14 tbrk13 tbrk12 tbrk11 tbrk10 tbrk9 tbrk8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 tbrk7 tbrk6 tbrk5 tbrk4 tbrk3 tbrk2 tbrk1 tbrk0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x29 -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 48. time break counter register timebrk bit definitions: 23:16 tbrk[23:16] time break counter upper byte 15:8 tbrk[15:8] time break counter middle byte 15:8 tbrk[7:0] time break counter lower byte
cs5378 ds639f1 78 20.2.7 tbscfg : 0x2a (msb) 23 22 21 20 19 18 17 16 intp7 intp6 intp5 intp4 intp3 intp2 intp1 intp0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 tmode rate2 rate1 rate0 tsync -- -- -- r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 loop run ddly5 ddly4 ddly3 ddly2 ddly1 ddly0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x2a -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 49. test bit stream configuration register tbscfg bit definitions: 23:16 intp[7:0] interpolation factor 0xff: 256 0xfe: 255 ... 0x01: 2 0x00: 1 (use once) 15 tmode operational mode 1: impulse mode 0: sine mode 7 loop loopback tbsdata output to mdata inputs 1: enabled 0: disabled 14:12 rate[2:0] tbsdata and tbsclk output rate. 111: 2.048 mhz 110: 1.024 mhz 101: 512 khz 100: 256 khz 011: 128 khz 010: 64 khz 001: 32 khz 000: 4 khz 6 run run test bit stream 1: enabled 0: disabled 11 tsync synchronization 1: sync enabled 0: no sync 5:0 ddly[5:0] tbsdata output delay 0x3f: 63 bits 0x3e: 62 bits ... 0x01: 1 bit 0x00: 0 bits ( no delay) 10:8 -- reserved
cs5378 ds639f1 79 20.2.8 tbsgain : 0x2b (msb) 23 22 21 20 19 18 17 16 tgain23 tgain22 tgain21 tgain20 tgain19 tgain18 tgain17 tgain16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 tgain15 tgain14 tgain13 tgain12 tgain11 tgain10 tgain9 tgain8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 tgain7 tgain6 tgain5 tgain4 tgain3 tgain2 tgain1 tgain0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x2b -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 50. test bit stream gain register tbsgain bit definitions: 23:16 tgain[23:16] test bit stream gain upper byte 15:8 tgain[15:8] test bit stream gain middle byte 15:8 tgain[7:0] test bit stream gain lower byte
cs5378 ds639f1 80 20.2.9 system1, system2 : 0x2c, 0x2d (msb) 23 22 21 20 19 18 17 16 sys23 sys22 sys21 sys20 sys19 sys18 sys17 sys16 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 15 14 13 12 11 10 9 8 sys15 sys14 sys13 sys12 sys11 sys10 sys9 sys8 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 7654321(lsb) 0 sys7 sys6 sys5 sys4 sys3 sys2 sys1 sys0 r/wr/wr/wr/wr/wr/wr/wr/w 00000000 df address: 0x2c -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 51. user defined system register system1 bit definitions: 23:16 sys[23:16] system register upper byte 15:8 sys[15:8] system register middle byte 15:8 sys[7:0] system register lower byte
cs5378 ds639f1 81 20.2.10 version : 0x2e (msb) 23 22 21 20 19 18 17 16 type7 type6 type5 type4 type3 type2 type1 type0 r/wr/wr/wr/wr/wr/wr/wr/w 01111000 15 14 13 12 11 10 9 8 hw7 hw6 hw5 hw4 hw3 hw2 hw1 hw0 r/wr/wr/wr/wr/wr/wr/wr/w 00000001 7654321(lsb) 0 rom7 rom6 rom5 rom4 rom3 rom2 rom1 rom0 r/wr/wr/wr/wr/wr/wr/wr/w 00000001 df address: 0x2e -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 52. hardware version id register version bit definitions: 23:16 type [7:0] chip type 78 - cs5378 15:8 hw [7:0] hardware revision 01 - cs5378 rev a 7:4 rom [7:0] rom version 01 - ver 1.0
cs5378 ds639f1 82 20.2.11 selftest : 0x2f (msb) 23 22 21 20 19 18 17 16 -- -- -- -- eu3 eu2 eu1 eu0 r/wr/wr/wr/wr/wr/wr/wr/w 00001010 15 14 13 12 11 10 9 8 dram3 dram2 dram1 dram0 pram3 pram2 pram1 pram0 r/wr/wr/wr/wr/wr/wr/wr/w 10101010 7654321(lsb) 0 drom3 drom2 drom1 drom0 prom3 prom2 prom1 prom0 r/wr/wr/wr/wr/wr/wr/wr/w 10101010 df address: 0x2f -- not defined; read as 0 r readable wwritable r/w readable and writable bits in bottom rows are reset condition figure 53. self test result register selftest bit definitions: 23:20 -- reserved 15:12 dram [3:0] data ram test ?a?: pass ?f?: fail 7:4 drom [3:0] data rom test ?a?: pass ?f?: fail 19:16 eu [3:0] execution unit test ?a?: pass ?f?: fail 11:8 pram [3:0] program ram test ?a?: pass ?f?: fail 3:0 prom [3:0] program rom test ?a?: pass ?f?: fail
cs5378 ds639f1 83 21. pin description 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 gpio0 gpio1 gpio2 gpio3 gpio4:pll0 gpio5:pll1 gpio6:pll2 tbsdata vddpad gndpad mclk msync mdata mflag gpio7:boot ss:eecs mosi miso sck drdy gndcore vddcore timeb sync reset clk gndpll vddpll figure 54. cs5378 pin assignments pin name pin number pin type pin description general purpose input / output gpio[0:3] 1, 2, 3, 4 input / output general purpose i/o. gpio[4:6]:pll[0:2] 5, 6, 7 input / output general purpose i/o with pll mode select. gpio pins have weak (~100 k ? ) internal pullups. pll mode selection latched immediately after reset. gpio7:boot 28 input / output general purpose i/o with boot mode select. gpio pins have weak (~100 k ? ) internal pullups. boot mode selection latched immediately after reset. pll[2:0] reset mode 111 32.768 mhz clock input (pll bypass). 110 1.024 mhz clock input. 101 2.048 mhz clock input. 100 4.096 mhz clock input. 011 32.768 mhz clock input (pll bypass). 010 1.024 mhz manchester input. 001 2.048 mhz manchester input. 000 4.096 mhz manchester input. boot reset mode 1 eeprom boot 0 microcontroller boot
cs5378 ds639f1 84 pin name pin number pin type pin description test bit stream tbsdata 8 output test bit stream data output. modulator interface mclk 11 output modulator clock output. msync 12 output modulator sync output. mdata 13 input modulator data input. mflag 14 input modulator flag input. telemetry interface clk 17 input clock input. reset 18 input reset, active low. sync 19 input sync input. timeb 20 input time break input. serial interface drdy 23 output data ready, active low. sck 24 input / output serial clock. miso 25 input / output serial data, master in / slave out. mosi 26 input / output serial data, master out / slave in. ss:eecs 27 input slave select with eeprom chip select, active low. power supplies vddpad, gndpad 9, 10 supply pin power supply. vddpll, gndpll 15, 16 supply pll power supply. vddcore, gndcore 21, 22 supply logic core power supply.
cs5378 ds639f1 85 22.package dimensions inches millimeters note dim min nom max min nom max a-- --0.084-- --2.13 a1 0.002 0.006 0.010 0.05 0.15 0.25 a2 0.064 0.069 0.074 1.62 1.75 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.390 0.4015 0.413 9.90 10.20 10.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.0354 0.041 0.63 0.90 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters 28l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5378 ds639f1 86 23.ordering information 24.environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 25.revision history model temperature package CS5378-IS -40 to +85 c 28-pin ssop CS5378-ISz lead free model number peak reflow temp msl rating* max floor life CS5378-IS 240 c 2365 days CS5378-ISz lead free 260 c 3 7 days revision date changes pp1 feb 2004 initial ?prelim inary product? release. f1 oct 2005 added lead-free device ordering information. added msl data. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus pro ducts are not designed, author ized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other crit ical applications. inclusio n of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer u ses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

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